Thu, Dec 16 AM
Chair: Ryuichi Fujimoto (STARC)
09:30 - 11:45 |
| (1) |
09:30-09:55 |
Elimination of Half Select Disturb in 8T-SRAM by Local Injected Electron Asymmetric Pass Gate Transistor |
Kentaro Honda, Kousuke Miyaji, Shuhei Tanakamaru (Univ. of Tokyo), Shinji Miyano (STARC), Ken Takeuchi (Univ. of Tokyo) |
| (2) |
09:55-10:45 |
[Invited Talk]
How to Write ISSCC Paper at Keio Kuroda Laboratory |
Noriyuki Miura (Keio Univ.) |
| |
10:45-10:55 |
Break ( 10 min. ) |
| (3) |
10:55-11:45 |
[Invited Talk]
Ambient Electronics and Integrated Circuits |
Takayasu Sakurai (Tokyo Univ.) |
| |
11:45-13:00 |
Lunch hour ( 75 min. ) |
Thu, Dec 16 PM
Chair: Takehiko Amaki (Osaka Univ.)
13:00 - 14:15 |
| (4) |
13:00-13:50 |
[Invited Talk]
Measurement and Characteristics Validation of On-chip Signal and Power Noise
-- Looking back on my doctoral course -- |
Yasuhiro Ogasahara (Renesas Electronics Corp.) |
| (5) |
13:50-14:15 |
High Error Rate Compensation Architecture and ECC for SSDs with NV-RAM and NAND Flash |
Kazuhide Higuchi, Mayumi Fukuda, Shuhei Tanakamaru, Ken Takeuchi (Univ. Tokyo) |
| |
14:15-14:25 |
Break ( 10 min. ) |
Thu, Dec 16 PM Poster session
14:25 - 17:30 |
| (6) |
14:25-14:55 |
Short Presentation |
| |
14:55-15:10 |
Break ( 15 min. ) |
| (7) |
15:10-17:10 |
[Poster Presentation]
CMOS-Based Nonvolatile Flip-Flop Design and its Application to a Fractional-N PLL Frequency Synthesizer |
Ge Wang, Jungyu Lee, Shoichi Masui (Tohoku Univ.) |
| (8) |
15:10-17:10 |
[Poster Presentation]
IF filter research for next generation wireless transceiver |
Ben Patrick, Takayuki Konishi, Toru Kashimura, Shoichi Masui (Tohoku Univ.) |
| (9) |
15:10-17:10 |
[Poster Presentation]
Chip Development of Ubiquitous Processor |
Harunobu Uchiumi, Takumi Ishihara, Naomichi Mimura, Kazuki Narita, Tatsuya Takaki, Masa-aki Fukase, Tomoaki Sato (Hirosaki Univ.) |
| (10) |
15:10-17:10 |
[Poster Presentation]
A 0.5V Subthreshold CMOS Analog Amplifier with Sub-MHz Bandwidth |
Takashi Mori, Tomochika Harada, Koichi Matsushita, Sumio Okuyama (Yamagata Univ.) |
| (11) |
15:10-17:10 |
[Poster Presentation]
A 65nm CMOS High-Speed and High-Fidelity NBTI Recovery Sensor |
Takashi Matsumoto, Hiroaki Makino (Kyoto Univ.), Kazutoshi Kobayashi (Kyoto Inst. Tech.), Hidetoshi Onodera (Kyoto Univ.) |
| (12) |
15:10-17:10 |
[Poster Presentation]
Study on CMOS R-2R Ladder for Linearity Optimization by Adjust Channel Width |
Yuta Kato, Cong-Kha Pham (UEC) |
| (13) |
15:10-17:10 |
[Poster Presentation]
A Charge Sampling Filter with Second Order Sinc for SDR Receiver |
Kenji Minefuji, Takashi Matsumoto (Waseda Univ.) |
| (14) |
15:10-17:10 |
[Poster Presentation]
A Study of Pull-in Lock Simulation in CDR-PLL |
Yasuyuki Shimizu (Osaka Inst. Tech.), Tsutomu Yoshimura, Shuhei Iwade, Hiroshi Makino (OIT), Yoshio Matsuda (Kanazawa Univ.) |
| (15) |
15:10-17:10 |
[Poster Presentation]
Comparison and Analysis of the Noise Sensitivity between LC-tank and Ring-type VCO |
Ken Maruhashi, Tsutomu Yoshimura, Shuhei Iwade, Hiroshi Makino (Osaka Inst. Tech.), Yoshio Matsuda (Kanazawa Univ.) |
| (16) |
15:10-17:10 |
[Poster Presentation]
Evaluation of Power Gating Structures Focusing on Power Supply Noise with Measurement and Simulation |
Yasumichi Takai, Masanori Hashimoto, Takao Onoye (Osaka Univ.) |
| (17) |
15:10-17:10 |
[Poster Presentation]
A 0.5V 6-bit Scalable Phase Interpolator |
Satoshi Kumaki, Abul Hasan Johari, Takeshi Matsubara (Keio Univ), Isamu Hayashi (STARC), Hiroki Ishikuro (Keio Univ) |
| (18) |
15:10-17:10 |
[Poster Presentation]
Design of Triple-band GPS Receiver |
Ikkyun Jo, Toshimasa Matsuoka, Kenji Taniguchi (Osaka Univ.), Takuji Ebinuma (The Univ. of Tokyo) |
| (19) |
15:10-17:10 |
[Poster Presentation]
Evaluation of power noise in SRAM core |
Taku Toshikawa, Tsubasa Masui, Takuya Sawada, Makoto Nagata (Kobe Univ.) |
| (20) |
15:10-17:10 |
[Poster Presentation]
MOS SPICE Model Evaluation Based on gm/Id Lookup Table Methodology |
Kenji Inazu, Toru Kashimura, Takayuki Konishi (Tohoku Univ.), Takana Kaho (NTT), Shoichi Masui (Tohoku Univ.) |
| (21) |
15:10-17:10 |
[Poster Presentation]
Design of Memory Access Controller for FU Array Accelerator |
Shunsuke Shitaoka, Takuya Iwakami, Kazuhiro Yoshimura, Takashi Nakada, Yasuhiko Nakashima (NAIST) |
| (22) |
15:10-17:10 |
[Poster Presentation]
Design of An FU Network for Array Accelerators |
Suguru Ooue, Takuya Iwakami, Kazuhiro Yoshimura, Takashi Nakada, Yasuhiko Nakashima (NAIST) |
| (23) |
15:10-17:10 |
[Poster Presentation]
On-chip immunoassay by a standard CMOS chip |
Jaesung Lee (Hiroshima Univ.), Koh Johguchi (Univ. of Tokyo), Fumie Kaneko (Astellas), Tomohiro Ishikawa (Hiroshima Univ.) |
| (24) |
17:10-17:30 |
|
Fri, Dec 17 AM
Chair: Shinji Miyano (STARC)
09:30 - 11:45 |
| (25) |
09:30-10:20 |
[Invited Talk]
Time Difference Amplifier, from Getting Idea to Presenting at a Conference |
Toru Nakura (Univ. of Tokyo) |
| (26) |
10:20-10:45 |
Low Power and Highly Reliable Ferroelectric (Fe)-NAND Flash Memory for Enterprise SSD |
Teruyoshi Hatanaka, Ryoji Yajima, Shinji Noda (Univ. of Tokyo), Mitsue Takahashi, Shigeki Sakai (AIST), Ken Takeuchi (Univ. of Tokyo) |
| |
10:45-10:55 |
Break ( 10 min. ) |
| (27) |
10:55-11:20 |
Development of Procedure for Modeling MOSFET Compatible with ITRS
-- Noise and I-V Characteristics Modeling for RF/Analog MOSFET -- |
Sin-Nyoung Kim, Akira Tsuchiya, Hidetoshi Onodera (Kyoto Univ.) |
| (28) |
11:20-11:45 |
A Charge-Domain Auto- and Cross-Correlation Based IR-UWB Receiver with Power- and Area-efficient PLL for 62.5ps Step Data Synchronization in 65nm CMOS |
Lechang Liu, Takayasu Sakurai, Makoto Takamiya (Univ. of Tokyo) |
| |
11:45-13:00 |
Lunch hour ( 75 min. ) |
Fri, Dec 17 PM
Chair: Takashi Matsumoto (Kyoto Univ.)
13:00 - 14:40 |
| (29) |
13:00-13:50 |
[Invited Talk]
Variability in Scaled MOS Devices |
Kiyoshi Takeuchi (Renesas) |
| (30) |
13:50-14:15 |
Misleading Energy and Performance Claims in Sub/Near Threshold Digital Systems |
Yu Pu, Xin Zhang, Jim Huang (Univ. of Tokyo), Atsushi Muramatsu, Masahiro Nomura, Koji Hirairi, Hidehiro Takata, Taro Sakurabayashi, Shinji Miyano (STARC), Makoto Takamiya, Takayasu Sakurai (Univ. of Tokyo) |
| (31) |
14:15-14:40 |
Fine Grained Time Sharing to Extend Capacity of FU Array |
Takuya Iwakami, Kazuhiro Yoshimura, Kodai Mori, Takashi Nakada, Yasuhiko Nakashima (NAIST) |
| |
14:40-14:50 |
Break ( 10 min. ) |
Fri, Dec 17 PM
Chair: Tadashi Yasufuku (Univ. Tokyo), Akira Shikara (Keio Univ.)
14:50 - 17:05 |
| (32) |
14:50-15:15 |
Comparison of the Error Correction Methods for SSDs and Dynamic Codeword Transition ECC Scheme |
Shuhei Tanakamaru (Univ. of Tokyo), Atsushi Esumi, Mitsuyoshi Ito, Kai Li (SIGLEAD), Ken Takeuchi (Univ. of Tokyo) |
| (33) |
15:15-15:40 |
A Circuit Partitioning Strategy for 3-D Integrated Multipliers |
Kazuhito Sakai, Jubee Tada (Yamagata Univ.), Ryusuke Egawa, Hiroaki Kobayashi (Tohoku Univ.), Gensuke Goto (Yamagata Univ.) |
| (34) |
15:40-16:05 |
Design of a Low Error LUT-based Truncated Multiplier |
Van-Phuc Hoang, Cong-Kha Pham (Univ. of Electro-comm.) |
| |
16:05-16:15 |
Break ( 10 min. ) |
| (35) |
16:15-16:40 |
A 1-V Input, 0.2-V to 0.47-V Output Switched-Capacitor DC-DC Converter with Pulse Density and Width Modulation (PDWM) for 57% Ripple Reduction |
Xin Zhang, Yu Pu, Koichi Ishida (Univ. of Tokyo), Yoshikatsu Ryu, Yasuyuki Okuma (STARC), Po-Hung Chen (Univ. of Tokyo), Kazunori Watanabe (STARC), Takayasu Sakurai, Makoto Takamiya (Univ. of Tokyo) |
| (36) |
16:40-17:05 |
0.18-V Input Charge Pump with Forward Body Biasing in Startup Circuit using 65nm CMOS |
Po-Hung Chen, Koichi Ishida, Xin Zhang (Tokyo Univ.), Yasuyuki Okuma, Yoshikatsu Ryu (STARC), Makoto Takamiya, Takayasu Sakurai (Tokyo Univ.) |
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