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Technical Committee on Reconfigurable Systems (RECONF)
Chair: Moritoshi Yasunaga (Univ. of Tsukuba) Vice Chair: Shorin Kyo (Renesas), Minoru Watanabe (Shizuoka Univ.)
Secretary: Nobuya Watanabe (Okayama Univ.), Yutaka Yamada (Toshiba)
Assistant: Yoshiki Yamaguchi (Univ. of Tsukuba)
DATE:
Tue, Sep 18, 2012 09:30 - 17:20
Wed, Sep 19, 2012 09:00 - 15:30
PLACE:
Epock Ritsumei 21, Ritsumeikan Univ.(1-1-1 Noji-higashi, Kusatsu Shiga 525-8577 JAPAN. http://www.ritsumei.ac.jp/eng/. Prof. Tomonori IZUMI)
TOPICS:
Reconfigurable Systems, etc.
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Tue, Sep 18 AM (09:30 - 10:45)
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(1) 09:30 - 09:55
FPGA-based video stabilisation
Toru Yabuki, Yoshiki Yamaguchi, Yuetsu Kodama (Univ. of Tsukuba)
(2) 09:55 - 10:20
A development of trafic-sign recognition system by using vector processor Venice
Yoshiya Sugita, Tomoki Tomisawa, Masahiro Fukui (Ritsumeikan Univ.)
(3) 10:20 - 10:45
JPEG encoder design improvement and its evaluation for Dynamic Reconfigurable Circuit
Hajime Sawano, Nobuyuki Araki, Takashi Kambe (Kinki Univ.)
----- Break ( 25 min. ) -----
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Tue, Sep 18 AM (11:10 - 12:00)
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(4) 11:10 - 11:35
An approach for generating new timbres by the use of an FPGA
Suguru Ochiai, Yoshiki Yamaguchi, Yuetsu Kodama (Univ. of Tsukuba)
(5) 11:35 - 12:00
An Implementation and Evaluation of SOC Estimation System for Lithium-ion Battery by PSoC
Masashi Fujimoto, Tatsuya Inoue, Lei Lin, Masahiro Fukui (Ritsumeikan Univ.)
----- Break ( 80 min. ) -----
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Tue, Sep 18 PM (13:20 - 14:10)
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(6) 13:20 - 14:10
[Invited Talk]
The LSI Design Methodology of Tamper Resistant Cryptographic Circuit
Takeshi Fujino, Mitsuru Shiozaki, Takaya Kubota (Ritsumeikan Univ.), Masaya Yoshikawa (Meijyo Uiv.)
----- Break ( 15 min. ) -----
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Tue, Sep 18 PM (14:25 - 15:40)
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(7) 14:25 - 14:50
Area-Efficeint Design of Asynchronous Circuits Based on Balsa Framework for Synchronous FPGAs
Masanori Hariyama, Yoshiya Komatsu, Michitaka Kameyama (Tohoku Univ.)
(8) 14:50 - 15:15
Architecture of an Asynchronous FPGA for Handshake-Component-Based Design
Masanori Hariyama, Yoshiya Komatsu, Michitaka Kameyama (Tohoku Univ.)
(9) 15:15 - 15:40
An Area Minimized Logic Cluster using COGRE Logic Cell
Toshiya Takahashi, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
----- Break ( 25 min. ) -----
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Tue, Sep 18 PM (16:05 - 17:20)
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(10) 16:05 - 16:30
Castle of Chips: A reconfigurable technique for multiple chips implementation
Hideharu Amano (Keio Univ.)
(11) 16:30 - 16:55
Study of "fine-grain dynamic partial reconfiguration mechanism" on FPGA
Kunihiro Ueda, Naoki Kawamoto, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.)
(12) 16:55 - 17:20
Superimposing configuration acceleration method of an optically reconfigurable gate array including a speed adjustment bit
Takashi Yoza, Minoru Watanabe (Shizuoka Univ.)
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Wed, Sep 19 AM (09:00 - 10:15)
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(13) 09:00 - 09:25
Effects of Power Saving by Dynamic Partial Reconfiguration in Video Shape Detection Processing
Naoki Kawamoto, Kunihiro Ueda, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.)
(14) 09:25 - 09:50
Fast Flaw Detection of Liquid Crystal Glass with a FPGA Board
Keisuke Matsuyama, Lin Meng, Yasuo Tenjo, Katsuhiro Yamazaki (Ritsumeikan Univ.)
(15) 09:50 - 10:15
Gray-level image detection of a dynamically reconfigurable vision-chip architecture
Yuki Kamikubo, Minoru Watanabe, Shoji Kawahito (Shizuoka Univ.)
----- Break ( 25 min. ) -----
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Wed, Sep 19 AM (10:40 - 11:55)
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(16) 10:40 - 11:05
Low-Power Heterogeneous Platform for High Performance Computing and Its Application to 2-D FDTD Computation
Masanori Hariyama, Hasitha Muthumala Waidyasooriya, Yasuhiro Takei, Michitaka Kameyama (Tohoku Univ.)
(17) 11:05 - 11:30
Prototyping Tightly-Coupled FPGA Cluster for Lattice Boltzmann Computation
Kentaro Sano, Yoshiaki Kono, Hayato Suzuki, Ryotaro Chiba, Satoru Yamamoto (Tohoku Univ.)
(18) 11:30 - 11:55
OS for Multiple FPGA Clusters which have Different Communication Interfaces
Akira Kojima, Tetsuo Hironaka (Hiroshima City Univ.)
----- Break ( 80 min. ) -----
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Wed, Sep 19 PM (13:15 - 14:05)
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(19) 13:15 - 13:40
A Design Framework for Reconfigurable IPs with VLSI CADs
Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
(20) 13:40 - 14:05
A Circuit Synthesis Algorithm and Evaluation for Coarse Grained Dynamic Reconfigurable Circuits
Nobuyuki Araki, Takashi Kambe (Kinki Univ.)
----- Break ( 25 min. ) -----
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Wed, Sep 19 PM (14:15 - 15:30)
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(21) 14:15 - 14:40
An implementation and evaluation of variable speed charger for lithium-ion battery by PSoC
Satoshi Aoki, Takahito Hirata, Masahiro Fukui (Ritsumeikan Univ.)
(22) 14:40 - 15:05
A Virus Scanning Engine Using an MPU and an IGU Based on ROW Shift Decomposition
Hiroki Nakahara (Kaoghima Univ.), Tsutomu Sasao, Munehiro Matsuura (KIT)
(23) 15:05 - 15:30
Speedup of soft error tolerance evaluation with bootstrap method for FPGA systems
Kohei Takano, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
# Information for speakers
General Talk will have 20 minutes for presentation and 5 minutes for discussion.
=== Technical Committee on Reconfigurable Systems (RECONF) ===
# SECRETARY:
Minoru Watanabe (Shizuoka Univ.)
E-mail: tmwatan [atmark] ipc.shizuoka.ac.jp
TEL: +81-53-478-1096
FAX: +81-53-478-1096
Last modified: 2012-09-08 14:49:22
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