Wed, Mar 2 PM
13:10 - 14:50 |
| (1) |
13:10-13:35 |
An Architecture Exploration Method based on a Branch-and-Bound Strategy for Embedded VLIW Processors |
Kohei Aoki, Ittetsu Taniguchi, Hiroyuki Tomiyama, Masahiro Fukui (Ritsumeikan Univ.) |
| (2) |
13:35-14:00 |
Energy-Aware Instruction Scheduling for Fine-Grained Power-Gated VLIW Processors with Multi-Cycle Instructions |
Mitsuya Uchida, Ittetsu Taniguchi, Hiroyuki Tomiyama, Masahiro Fukui (Ritsumeikan Univ.) |
| (3) |
14:00-14:25 |
Exact, Fast and Flexible Two-level Cache Simulation for Embedded Systems |
Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa (Waseda Univ.) |
| (4) |
14:25-14:50 |
Intra-task Analysis of Worst Case Execution Time and Average Energy Consumption on DEPS Framework |
Hirotaka Kawashima, Gang Zeng, Noritoshi Atsumi, Tomohiro Tatematsu, Hiroaki Takada (Nagoya Univ.) |
| |
14:50-15:05 |
Break ( 15 min. ) |
Wed, Mar 2 PM
15:05 - 16:45 |
| (5) |
15:05-15:30 |
An Energy-efficient ASIP Synthesis Method Using Scratchpad Memory and Code Placement Optimization |
Yoshinori Shimada, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) |
| (6) |
15:30-15:55 |
Investigation and Evaluation of Sleep Signal Control based on a History Information for Fine-grain Power Gating |
Tetsuya Muto, Kimiyoshi Usami (Shibaura Inst. of Tech.) |
| (7) |
15:55-16:20 |
Low Power Design of Digital Circuits using Quasi-complementary MOS Gates |
Shuichi Sowa, Mineo Kaneko (JAIST) |
| (8) |
16:20-16:45 |
Reusable Constraints of Nano-watt BGR Circuits in CMOS Process Migration |
Gong Chen, Delong Yin, Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake (Univ. of Kitakyushu) |
| |
16:45-17:00 |
Break ( 15 min. ) |
Wed, Mar 2 PM
17:00 - 18:00 |
| (9) |
17:00-18:00 |
[Fellow Memorial Lecture]
Understanding CMOS Variability for More Moore |
Hidetoshi Onodera (Kyoto Univ./JST) |
Thu, Mar 3 AM
09:55 - 11:10 |
| (10) |
09:55-10:20 |
Semi-static TSPC DFF Using Split-output Latch |
Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo (Mie Univ.) |
| (11) |
10:20-10:45 |
Implementation and Security Evaluation of DPA-Resistant DES Circuit utilizing Domino-RSL technique |
Katsuhiko Iwai, Kenji Kojima, Mitsuru Shiozaki, Syunsuke Asagawa, Takeshi Fujino (Ritsumeikan Univ.) |
| (12) |
10:45-11:10 |
Evaluation of Delay-Time Difference Distribution for the Delay-Time Difference Measurable Arbiter-PUF |
Takahiko Murayama, Mitsuru Shiozaki, Kota Furuhashi, Akitaka Fukushima, Takeshi Fujino (Ritsumeikan Univ.) |
| |
11:10-11:25 |
Break ( 15 min. ) |
Thu, Mar 3 AM
11:25 - 12:15 |
| (13) |
11:25-11:50 |
A Low Power Hardware Architecture for Parallel Group Signature Computation |
Sumio Morioka, Jun Furukawa, Kazue Sako (NEC) |
| (14) |
11:50-12:15 |
A scalable hardware architecture for real time image recognition |
Takashi Aoki, Eiichi Hosoya, Takuya Otsuka, Akira Onozawa (NTT) |
Thu, Mar 3 PM
13:45 - 15:25 |
| (15) |
13:45-14:10 |
A Circuit Synthesis for High Speed Memory Access in System LSI |
Kazuya Kishida, Takashi Kambe (Kinki Univ.) |
| (16) |
14:10-14:35 |
A Circuit Synthesis for Dynamic Reconfigurable Processor |
Nobuyuki Araki, Takashi Kambe (Kinki Univ.) |
| (17) |
14:35-15:00 |
A Circuit Design and Its Evaluation for Correlation Caluculation in Particle Tracking System |
Shouta Moriguchi, Takashi Kambe (Kinki Univ.) |
| (18) |
15:00-15:25 |
Delay Variation-Aware Datapath Synthesis for Improved Performance and Tunability |
Dang Yu, Mineo Kaneko (JAIST) |
| |
15:25-15:40 |
Break ( 15 min. ) |
Thu, Mar 3 PM
15:40 - 16:55 |
| (19) |
15:40-16:05 |
A Study for Evaluation of Statistical Maximum Operations for Gaussian Mixture Models |
Tamotsu Ishihara, Masahiro Fukui (Ritsumeikan Univ.), Shuji Tsukiyama (Chuo Univ.) |
| (20) |
16:05-16:30 |
Performance Evaluation of Statistical Static Timing Analysis Using Gaussian Mixture Models |
Tomoyuki Fujimori, Shuji Tsukiyama (Chuo Univ), Masahiro Fukui (Ritsumeikan Univ) |
| (21) |
16:30-16:55 |
Delay Analysis of Sub-Path on Fabricated Chips by Several Path-delay Tests |
Takanobu Shiki, Yasuhiro Takashima (Univ.of Kitakyushu), Yuichi Nakamura (NEC Corp.) |
Fri, Mar 4 AM
10:00 - 11:40 |
| (22) |
10:00-10:25 |
A Routing Method for Multi-Layer Single Flux Quantum Circuits with Wire Ordering based on Slack Allocation |
Shota Takeshima, Kazuyoshi Takagi, Masamitsu Tanaka (Nagoya Univ.), Naofumi Takagi (Kyoto Univ.) |
| (23) |
10:25-10:50 |
CRP : Efficient Topology Modification for Minimum Perturbation Placement Realization |
Yuki Kouno, Yasuhiro Takashima (Univ. of Kitakyushu), Atsushi Takahashi (Osaka Univ.) |
| (24) |
10:50-11:15 |
Fast Algorithm for All-Pair Shortest Path on DAG using CUDA |
Akihide Yamamura, Yasuhiro Takashima (Univ. of Kitakyushu) |
| (25) |
11:15-11:40 |
On Realization and Evaluation of Capacitors in Analog Integrated Circuits |
Atsushi Ochi, Ryoei Shimazu, Toru Fujimura, Shigetoshi Nakatake (Univ.of Kitakyushu) |
Fri, Mar 4 PM
13:10 - 14:50 |
| (26) |
13:10-13:35 |
An evaluation of error detection/correction circuits by gate level simulation |
Masafumi Inoue (Tokyo Tech.), Yuuta Ukon, Atsushi Takahashi (Osaka Univ.) |
| (27) |
13:35-14:00 |
Behavior Verification of a Variable Latency Circuit on FPGA |
Yuuta Ukon (Osaka Univ), Masafumi Inoue (Tokyo Tech), Atsushi Takahashi, Kenji Taniguchi (Osaka Univ) |
| (28) |
14:00-14:25 |
Acceleration of Bounded Model Checking for Sequential Circuits with Two-phase Verification |
Norihiro Ono, Kazuhiro Nakamura, Kazuyoshi Takagi (Nagoya Univ.), Naofumi Takagi (Kyoto Univ.) |
| (29) |
14:25-14:50 |
Write Optimization for High-speed Non-volatile Memory Using Next State Function |
Naoya Okada (Waseda Univ.), Yuichi Nakamura (NEC), Shinji Kimura (Waseda Univ.) |
| |
14:50-15:05 |
Break ( 15 min. ) |
Fri, Mar 4 PM
15:05 - 16:20 |
| (30) |
15:05-15:30 |
A scalable prototyping system for 3D-stacked LSI development |
Marco Chacin, Hiroyuki Uchida, Michiya Hagimoto, Takashi Miyazaki, Takeshi Ohkawa, Rimon Ikeno, Yukoh Matsumoto (TOPS Systems), Fumito Imura, Katsuya Kikuchi, Motohiro Suzuki, Hiroshi Nakagawa, Masahiro Aoyagi (AIST) |
| (31) |
15:30-15:55 |
Performance Evaluation of Via Programmable ASIC Architecture VPEX3 |
Taisuke Ueoka, Tatsuya Kitamori, Ryohei Hori (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Takeshi Fujino (Ritsumeikan Univ.) |
| (32) |
15:55-16:20 |
Evaluation of Wiring Resource and Wiring Delay used in Via Programmable Logic Device VPEX |
Tatsuya Kitamori, Ryohei Hori, Taisuke Ueoka (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Takeshi Fujino (Ritsumeikan Univ.) |
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