Wed, Aug 9 AM 11:00 - 12:15 |
(1) |
11:00-11:25 |
Demonstration of Quantum Flux Parametron without DC Offset Currents using Ferromagnets |
Hayato Iwashita, Hiroshi Ito, Soya Taniguchi, Masamitsu Tanaka, Akira Fujimaki (Nagoya Univ.) |
(2) |
11:25-11:50 |
Energy evaluation of the feedback latch using AQFP logic |
Mai Nozoe, Naoki Takeuti, Christopher Ayala, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama National Univ.) |
(3) |
11:50-12:15 |
Yield Evaluation of 90k Junction-scale Adiabatic Quantum-Flux-Parametron Circuits |
Fumihiro China, Naoki Takeuchi, Yuki Yamanashi, Nobuyuki Yoshikawa (YNU) |
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12:15-13:20 |
Lunch Break ( 65 min. ) |
Wed, Aug 9 PM 13:20 - 15:00 |
(4) |
13:20-13:45 |
Evaluation of a random access memory cell composed of quantum flux parametron |
Hiroshi Takayama, Naoki Takeuchi, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama National Univ.) |
(5) |
13:45-14:10 |
Design and evaluation of 2 × 2 look-up table and extension to 4 × 4 for realization of FPGA using single flux quantum circuits |
Mika Araki, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama National Univ.) |
(6) |
14:10-14:35 |
Demonstration of AQFP/CMOS hybrid system and design and measurement of an AQFP 16-bit MUX |
Yukihiro Okuma, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama National Univ.) |
(7) |
14:35-15:00 |
Design of Component Circuits for Rapid Single-Flux-Quantum Gate-Level-Pipelined Microprocessors |
Yuki Hatanaka, Yuichi Matsui, Masamitsu Tanaka, Kyosuke Sano, Akira Fujimaki (Nagoya Univ.), Koki Ishida, Takatsugu Ono, Koji Inoue (Kyushu Univ.) |
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15:00-15:15 |
Break ( 15 min. ) |
Wed, Aug 9 PM 15:15 - 16:30 |
(8) |
15:15-15:40 |
Improvement of double oscillator type SFQ time-to-digital converter and realization of high temporal resolution |
Yuma Tomitsuka, Yutaka Abe (Yokohama National Univ.), Nobuyuki Zen (NAIST), Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama National Univ.) |
(9) |
15:40-16:05 |
Design of Digital SQUID using sub-SFQ Feedback with High Sampling Rate |
Kosuke Okabe, Masato Naruse, Tohru Taino, Hiroaki Myoren (Saitama Univ.) |
(10) |
16:05-16:30 |
Design of Low-latency SFQ Up/Down Counter for Digital Signal Processing |
Ryotaro Kamiya, Masato Naruse, Tohru Taino, Hiroaki Myoren (Saitama Univ.) |
Thu, Aug 10 AM 09:00 - 12:15 |
(11) |
09:00-10:30 |
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10:30-10:45 |
Break ( 15 min. ) |
(12) |
10:45-12:15 |
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12:15-13:15 |
Lunch Break ( 60 min. ) |
Thu, Aug 10 PM 13:15 - 16:30 |
(13) |
13:15-14:45 |
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14:45-15:00 |
Break ( 15 min. ) |
(14) |
15:00-16:30 |
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16:30-16:45 |
( 15 min. ) |