Online edition: ISSN 2432-6380
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RECONF2022-79
Multi-FPGA design environment using Cyberworkbench, a high-level synthesis tool
Hiroaki Suzuki (Keio Univ), Wataru Takahashi (NEC), Kazutoshi Wakabayashi (Tokyo Univ), Hideharu Amano (Keio Univ)
pp. 1 - 6
RECONF2022-80
Partitioning and Distributing Circuit Using HLS Split Compilation Tool for Reconfigurable Virtual Accelerator (ReVA)
Kazuki Yaguchi, Eriko Maeda, Daichi Teruya (TUAT), Yasunori Osana (Univ. of the Ryukyus), Takefumi Miyoshi (WasaLabo), Hironori Nakajo (TUAT)
pp. 7 - 12
RECONF2022-81
Initial Evaluation of FPGA Logic Element Placement Method Using Feature Extraction with Autoencoder
Junpei Sanuki, Ibuki Watanabe, Atsushi Kubota, Tetsuo Hironaka (HCU)
pp. 13 - 18
RECONF2022-82
Evaluation of reduced routing resources for HPC-Oriented CGRAs
Carlos Cortes, Boma Adhi, Tomohiro Ueno (RIKEN Center for Computational Science (R-CCS)), Yiyu Tan (Dept of Systems Innovation Engineering Iwate Univ.), Takuya Kojima (Information Science and Technology The Univ. of Tokyo), Artur Podobas (KTH Royal Inst. of Technology), Kentaro Sato (RIKEN Center for Computational Science (R-CCS))
pp. 19 - 23
RECONF2022-83
[Invited Talk]
Can we say "No FPGA, No Smart City"?
-- Let's declare if we do a smart city, we need FPGAs. --
Hiroaki Nishi (Keio Univ.)
p. 24
RECONF2022-84
(See Japanese page.)
pp. 25 - 26
RECONF2022-85
Interface development for Python use of FPGA cluster ESSPER
Taiki Watanabe (TUT), Kentaro Sano (R-CCS), Yukinori Sato (TUT)
pp. 27 - 28
RECONF2022-86
A study on optimisation of Back Projection Processing of CT Images using FPGA
Jumpei Mano, Takaaki Miyajima (Meiji Univ), Peng Chen (AIST), Mohamed Wahib, Kentaro Sano (RIKEN)
pp. 29 - 30
RECONF2022-87
(See Japanese page.)
pp. 31 - 33
RECONF2022-88
Measurement results of soft error tolerance of LPDDR4 SDRAM and GDDR5 SDRAM
Motoki Kamibayashi, Kazutoshi Kobayashi (Kyoto Inst. of Tech.), Masanori Hashimoto (Kyoto Univ.)
pp. 34 - 39
RECONF2022-89
Study on Wireless Transmission Data Reduction Method and Its Implementation in Emotion Recognition System Using Electroencephalogram
Yuuki Harada, Daisuke Kanemoto, Tetsuya Hirose (Osaka Univ.)
pp. 40 - 44
RECONF2022-90
Multi-Droplet Routing based on a Shape-Dependent Velocity Model on MEDA Biochips
Chiharu Shiro (Ritsumeiakn Univ.), Hiroki Nishikawa (Osaka Univ.), Xiangbo Kong, Hiroyuki Tomiyama, Shigeru Yamashita (Ritsumeiakn Univ.)
pp. 45 - 49
RECONF2022-91
Efficient FPGA Implementation of Binarized Neural Networks Based on Generalized Parallel Counter Tree
Takahiro Tanigawa, Mugi Noda, Nagisa Ishiura (Kwansei Gakuin Univ.)
pp. 50 - 55
RECONF2022-92
Akinobu Tomori (Univ. Ryukyu), Yasunori Osana (Univ. Ryukyus)
pp. 56 - 61
RECONF2022-93
An Implementation of Generic IP-cores for Linux by Using VIRTIO Interface
Kota Asanuma (TUAT/e-trees), Takefumi Miyoshi (e-trees)
pp. 62 - 67
RECONF2022-94
Leveraging dynamic parameter for solution search acceleration in bio-inspired hardware SAT solver
Anh Hoang Ngoc Nguyen (Fujitsu ltd.)
pp. 68 - 73
RECONF2022-95
Implementing a quantum computer simulator Qulacs on FPGAs
Hideharu Amano, Wei Kaijie (Keio Univ.), Takefumi Miyoshi (Wasalab.), Yoshiki Yamaguchi, Ryohei Niwase (U.niv. of Tsukuba)
pp. 74 - 79
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.