IEICE Technical Report

Print edition: ISSN 0913-5685      Online edition: ISSN 2432-6380

Volume 119, Number 25

VLSI Design Technologies

Workshop Date : 2019-05-15 / Issue Date : 2019-05-08

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Table of contents

VLD2019-1
A study on replica topology and temperature assignment for Ising-Model based Solver via Parallel Tempering
Akira Dan, Takashi Sato (Kyoto Univ.)
pp. 7 - 12

VLD2019-2
Approximate Computing Technique Using Memoization and Simplified Multiplication
Yoshinori Ono, Kimiyoshi Usami (SIT)
pp. 13 - 18

VLD2019-3
Study of new stacked type logic circuit scheme with fabrication technology of 3D flash memory
Fumiya Suzuki, Shigeyoshi Watanabe (Shonan Inst. of Tech.)
pp. 19 - 23

VLD2019-4
SRAM-Based Synthesis for Multi-Output Gates
Xingming Le, Amir Masoud Gharehbaghi, Masahiro Fujita (The Univ. of Tokyo)
pp. 25 - 30

VLD2019-5
The real chip evaluation of Through Chip Interface IP for Renesas 65nm SOTB process
Hideharu Amano, Hideto Kayashima, Tsunaaki Shidei, Takuya Kojima (Keio Univ.)
pp. 31 - 36

VLD2019-6
[Invited Talk] Viaswitch FPGA for Energy Efficient Computing
Masanori Hashimoto (Osaka Univ.)
pp. 37 - 41

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan