Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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VLD2016-102
Fine-Grain Power Gating of MTJ-based Non-volatile Cache and Dynamic Selection Control for Storing Cache Lines
Shota Enokido, Kimiyoshi Usami (SIT)
pp. 1 - 6
VLD2016-103
A Nonvolatile Flip-Flop Circuit with a Split Store/Restore Architecture for Power Gating
Masaru Kudo, Kimiyoshi Usami (Shibaura Institute of Tech.)
pp. 7 - 12
VLD2016-104
Post-Silicon Delay Tuning Method for Power Reduction considering Yield Improvement
Hayato Mashiko, Yukihide Kohira (Univ. of Aizu)
pp. 13 - 18
VLD2016-105
High accuracy 8*8 approximate multiplier based on OR operation
Yi Guo, Heming Sun, Canran Jin, Shinji Kimura (Waseda Univ.)
pp. 19 - 24
VLD2016-106
A Design Technique for Approximate Circuits based on Artificial Neural Network
Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 25 - 30
VLD2016-107
Implementation of a Transformation tool from Synchronous RTL Models to Asynchronous RTL Models
Shogo Senba, Hiroshi Saito (UoA)
pp. 31 - 36
VLD2016-108
Generation of Optimum Screening Patterns for a Screening Circuit to Detect Network Intrusion
Tomoaki Hashimoto, Shinobu Nagayama, Masato Inagi, Shin'ichi Wakabayashi (Hiroshima City Univ.)
pp. 37 - 42
VLD2016-109
FiCC: Crosstalk Noise Hardened Metal Fringe Capacitor for High Integration
Naoyuki Miyagawa, Tomoya Kimura, Hiroyuki Ochi (Ritsumeikan Univ.)
pp. 43 - 47
VLD2016-110
Reliability enhancement of Hierarchical data reading circuit of Wafer scale mask ROM
Takaaki Yokoyama, Ochi Hiroyuki (Ritsumeikan Univ)
pp. 49 - 54
VLD2016-111
High-speed TPL Layout Decomposition Method based on Positive Semidefinite Relaxation using Polygon Clustering
Shohei Handa, Shimpei Sato, Atsushi Takahashi (Tokyo TECH)
pp. 55 - 60
VLD2016-112
Acceleration of a Hotspot Detection Method Based on Approximate String Matching for LSI Mask Pattern Using Table Reference
Shuma Tamagawa, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hirohima City Univ.)
pp. 61 - 66
VLD2016-113
Efficient Local Pattern Modification Method using FM Algorithm in LELE Double Patterning
Atsushi Ogashira, Shimpei Sato, Atsushi Takahashi (Tokyo TECH)
pp. 67 - 72
VLD2016-114
Partial Route Modification Method to Realize Target Equi-length on Single Layer PCB Routing
Shun Sugihara, Shimpei Sato, Atsushi Takahashi (Tokyo Tech)
pp. 73 - 78
VLD2016-115
[Invited Talk]
Accelerating an IoT Application by using CPU-FPGA tightly coupled architecture
Yuki Kobayashi, Yoshikazu Watanabe, Seiya Shibata, Takashi Takenaka, Takeo Hosomi, Yuichi Nakamura (NEC)
p. 79
VLD2016-116
[Invited Talk]
IP Timing Constraints Promotion Challenges
-- A method to automatically generate SoC Timing Constraints --
Tatsuya Nakae, Ichiro Shiihara (Socionext)
p. 81
VLD2016-117
[Invited Talk]
Fast Monte Carlo based timing yield calculation via line sampling
Hiromitsu Awano (UTokyo), Takashi Sato (Kyoto Univ.)
pp. 83 - 84
VLD2016-118
Resource Binding and Domain Assignment for Multi-Domain Clock Skew Aware High-Level Synthesis
Xiaoguang Li, Mineo Kaneko (JAIST)
pp. 85 - 90
VLD2016-119
Optimum Temperature Dependent Timing Skew for Temperature Aware Design
Makoto Soga, Mineo Kaneko (JAIST)
pp. 91 - 96
VLD2016-120
MILP Approach to Skew-Aware High Level Synthesis
Kai Shimura, Mineo Kaneko (JAIST)
pp. 97 - 102
VLD2016-121
An algorithm to compute covariance for finding distribution of the maximum
Daiki Azuma, Shuji Tsukiyama (Chuo Univ.), Masahiro Fukui (Ritsumeikan Univ.), Takashi Kambe (Kinki Univ.)
pp. 103 - 108
VLD2016-122
Dynamic Power Optimization for Asynchronous Circuits with Bundled-data Implementation based on the Mobility of Operations
Shunya Hosaka, Hiroshi Saito (Aizu Univ)
pp. 109 - 114
VLD2016-123
A precise state-of-charge estimation system of primary battery for IoT devices
Hirofumi Shioura, Naoki Yoshida, Lei Lin, Masahiro Fukui (Ritsumeikan Univ.)
pp. 115 - 120
VLD2016-124
Using model-based design for EV batteries perfect for system development
Tomoki Abe, Ryo Ueno, Lie Lin, Masahiro Fukui (Ritsumeikan Univ.)
pp. 121 - 126
VLD2016-125
A design method of nMOS dynamic shift registers for driver circuit of small liquid crystal display
Youngtai Kang, Shuji Tsukiyama, Shinji Higa (Chuo Univ.)
pp. 127 - 132
VLD2016-126
A Study on LSI implementation of FEC for high-speed optical transmission
Susumu Hirano, Kazuo Kubo, Hideo Yoshida, Kenji Ishii, Kenya Sugihara, Takashi Sugihara, Koji Miyanohana, Hirohide Nozaki, Noriyuki Minegishi (Mitsubishi Elec.)
pp. 133 - 138
VLD2016-127
Optimization of Parallel Prefix Adder Using Simulated Annealing
Takayuki Moto, Mineo Kaneko (JAIST)
pp. 139 - 144
VLD2016-128
An Approach to Logic Optimization Using Permissible Functions for Error-Tolerant Application
Shinya Iwasaki, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (Hiroshima City Univ.)
pp. 145 - 150
VLD2016-129
Effect on the Chip Area of Component Adjacency Constraint for Soft-Error Tolerant Datapaths
Junghoon Oh, Mineo Kaneko (JAIST)
pp. 151 - 156
VLD2016-130
Architecture of Multiply-Accumulate Operation with Stochastic Iteration
Tatsuyoshi Sugino, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (Hiroshima City Univ.)
pp. 157 - 162
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.