Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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SDM2011-71
Study of pattern area reduction with 3 dimensional transistor for logic circuit
Takahiro Kodama, Shigeyoshi Watanabe (SIT), Yu Hiroshima (Oi Electric)
pp. 1 - 6
SDM2011-72
Study of pattern area reduction for standard cell with planar and SGT transistor
Takahiro Kodama, Shigeyoshi Watanabe (SIT)
pp. 7 - 12
SDM2011-73
Study of pattern area for reconfigurable logic circuit with DG/CNT transistor
Takamichi Hayashi, Shigeyoshi Watanabe (SIT)
pp. 13 - 16
SDM2011-74
Power-Performance Estimation of Datta-Das Spin Transistor
Yoshiyuki Kondo, Shigeru Kawanaka, Kanna Adachi (Toshiba)
pp. 17 - 22
SDM2011-75
Plasma Doping and Laser Spike Annealing Technique for Steep SDE Formation in nano-scale MOSFET
Emiko Sugizaki, Toshitaka Miyata, Yasunori Oshima, Akira Hokazono, Kanna Adachi, Kiyotaka Miyano, Hideji Tsujii, Shigeru Kawanaka, Satoshi Inaba, Takaharu Itani, Toshihiko Iinuma, Yoshiaki Toyoshima (Toshiba)
pp. 23 - 27
SDM2011-76
[Invited Talk]
Ferroelectric Random Access Memory
-- Fundamentals, recent advancements and future --
Shoichiro Kawashima (FSL)
pp. 29 - 34
SDM2011-77
[Invited Talk]
Sub-nanowatt Circuit Techniques Enabling Wireless-sensor-node Operation with an Energy Harvester
Mamoru Ugajin, Toshishige Shimamura, Hiroki Morimura, Shin'ichiro Mutoh, Mitsuru Harada (NTT)
pp. 35 - 40
SDM2011-78
[Invited Talk]
A Wireless Self-powered Sensor with Ambient Energy Sources
Takakuni Douseki (Ritsumeikan Univ.)
pp. 41 - 46
SDM2011-79
A Low Power 90-nm CMOS Motion Estimation Processor Array Implementing Stick-shaped Search Window (SSW) Block Matching Algorithm
Tadayoshi Enomoto (Chuo Univ.)
pp. 47 - 52
SDM2011-80
Novel power reduction technique for ReRAM with the automatic evasion circuit of the wasteful overwrite
Takaya Handa, Kazuya Nakayama, Akio Kitagawa, Junichi Akita (Kanazawa Univ.)
pp. 53 - 57
SDM2011-81
[Invited Talk]
Applications/Market Trends of Energy Harvesting
Keiji Takeuchi (NTT Data Institute of Management Consulting)
pp. 59 - 61
SDM2011-82
[Panel Discussion]
Ultralow-power technologies for energy harvesting sensor network systems
Keiji Takeuchi (NTT Data BR), Mamoru Ugajin (NTT), Syouichirou Kawasaki (Fujitsu), Takakuni Douseki (Ritsu), Makoto Takamiya (U-Tokyo), Jiro Ida, Yuichi Kado (KIT)
p. 63
SDM2011-83
Evaluation of Variability in High-k/Metal-Gate MOSFET using Takeuchi Plot
Tomoko Mizutani, Anil Kumar (Univ. of Tokyo), Akio Nishida, Kiyoshi Takeuchi, Satoshi Inaba, Shiro Kamohara (MIRAI-Selete), Kazuo Terada (Hiroshima City Univ.), Tohru Mogami (MIRAI-Selete), Toshiro Hiramoto (Univ. of Tokyo/MIRAI-Selete)
pp. 65 - 68
SDM2011-84
Statistical Analysis of DIBL and Current-Onset Voltage (COV) Variability in Scaled MOSFETs
Anil Kumar, Tomoko Mizutani (Univ. of Tokyo), Akio Nishida, Kiyoshi Takeuchi, Satoshi Inaba, Shiro Kamohara (MIRAI-Selete), Kazuo Terada (Hiroshima City Univ.), Tohru Mogami (MIRAI-Selete), Toshiro Hiramoto (Univ. of Tokyo/MIRAI-Selete)
pp. 69 - 73
SDM2011-85
Phase-change memory driven by poly-Si MOS transistor with low cost and high-programming throughput
Yoshitaka Sasago, Masaharu Kinoshita, Hiroyuki Minemura, Yumiko Anzai, Mitsuharu Tai, Kenzo Kurotsuchi, Seiichi Morita, Toshikazu Takahashi, Takashi Takahama, Tadao Morimoto, Toshiyuki Mine, Akio Shima, Takashi Kobayashi (Hitachi)
pp. 75 - 78
SDM2011-86
[Invited Talk]
Status and Prospect of Ultra Low Power Logic Devices
Jiro Ida (KIT)
pp. 79 - 83
SDM2011-87
[Invited Talk]
Technology Trends in Low Power Digital Circuits
Masaya Sumita (Panasonic)
p. 85
SDM2011-88
[Invited Talk]
0.5V Extremely Low Power Circuits for Wireless Sensor Nodes with Energy Harvesting
Makoto Takamiya, Koichi Ishida, Hiroshi Fuketa (Univ. of Tokyo), Masahiro Nomura, Hirofumi Shinohara (STARC), Takayasu Sakurai (Univ. of Tokyo)
pp. 87 - 92
SDM2011-89
Ultra low noise in-substrate-bitline sense amplifier for 4F2 DRAM array
Yoshimitsu Yanagawa, Tomonori Sekiguchi, Akira Kotabe, Kazuo Ono, Riichiro Takemura (Hitachi)
pp. 93 - 97
SDM2011-90
Sense Amplifier with Current Control Switch for Small-sized 0.5-V Gigabit-DRAM Arrays
Akira Kotabe, Yoshimitsu Yanagawa, Riichiro Takemura, Tomonori Sekiguchi, Kiyoo Itoh (Hitachi)
pp. 99 - 102
SDM2011-91
Dependable SRAM with Enhanced Read-/Write-Margins by Fine-Grained Assist Bias Control for Low-Voltage Operation
Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Hirofumi Nakano, Kazuya Ishihara, Hiroyuki Kawai, Kazutami Arimoto (Renesas)
pp. 103 - 108
SDM2011-92
A 28-nm dual-port SRAM macro with active bitline equalizing circuitry against write disturb issue
Yuichiro Ishii, Hidehiro Fujiwara, Koji Nii (Renesas Electronics), Hideo Chigasaki, Osamu Kuromiya, Tsukasa Saiki (Renesas Design), Atsushi Miyanishi, Yuji Kihara (Renesas Electronics)
pp. 109 - 114
SDM2011-93
A Dynamic body-biased SRAM with Asymmetric Halo Implant MOSFETs
Makoto Yabuuchi, Yasumasa Tsukamoto, Hidehiro Fujiwara, Koji Maekawa, Motoshige Igarashi, Koji Nii (Renesas)
pp. 115 - 120
SDM2011-94
Reduction of Minimum Operating Voltage (VDDmin) of CMOS Logic Circuits with Post-Fabrication Automatically Selective Charge Injection
Kentaro Honda, Katsuyuki Ikeuchi (Univ. of Tokyo), Masahiro Nomura (STARC), Makoto Takamiya, Takayasu Sakurai (Univ. of Tokyo)
pp. 121 - 126
SDM2011-95
Energy Efficiency Increase of Integer Unit Enabled by Contention-less Flip-Flops (CLFF) and Separated Supply Voltage between Flip-Flops and Combinational Logics
Hiroshi Fuketa (Univ. of Tokyo), Koji Hirairi (STARC), Tadashi Yasufuku, Makoto Takamiya (Univ. of Tokyo), Masahiro Nomura, Hirofumi Shinohara (STARC), Takayasu Sakurai (Univ. of Tokyo)
pp. 127 - 132
SDM2011-96
Optimization of the low voltage operation Circuits for the Self-synchronous system
Ayumi Kamitani, Makoto Ikeda (Tokyo Univ.)
pp. 133 - 138
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.