Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
[TOP] | [2006] | [2007] | [2008] | [2009] | [2010] | [2011] | [2012] | [Japanese] / [English]
DC2008-28
On Improving Transition Fault Coverage of Stuck-at Fault Tests Using Don't Care Identification Technique
Kazumitsu Hamasaki, Toshinori Hosokawa (Nihon Univ.)
pp. 1 - 6
DC2008-29
An Integer Programming Formulation for Generating High Quality Transition Tests
Tsuyoshi Iwagaki, Mineo Kaneko (Japan Advanced Institute of Science and Technology)
pp. 7 - 12
DC2008-30
A Capture-Safe Test Generation Scheme for At-speed Scan Testing
Atsushi Takashima, Yuta Yamato, Hiroshi Furukawa, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyusyu Institute of Technology)
pp. 13 - 18
DC2008-31
Analysis of Open Fault using TEG Chip
Toshiyuki Tsutsumi, Yasuyuki Kariya, Koji Yamazaki (Meiji Univ), Masaki Hashizume, Hiroyuki Yotsuyanagi (Tokushima Univ), Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu (Ehime Univ)
pp. 19 - 24
DC2008-32
Area Efficient Multipliers Utilizing the Sum of Operands
Hirotaka Kawashima, Naofumi Takagi (Nagoya Univ.)
pp. 25 - 30
DC2008-33
Hardware Algorithm for Division in GF(2^m) Based on the Extended Euclid's Algorithm Accelerated with Parallelization of Modular Reductions
Katsuki Kobayashi, Naofumi Takagi (Nagoya Univ.)
pp. 31 - 36
DC2008-34
Multi-Rate Compatible High Throughput Irregular LDPC Decoder Based on High-Efficiency Column Operation Unit
Akiyuki Nagashima, Yuta Imai, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
pp. 37 - 42
DC2008-35
A Parallel Hardware Engine for Generating Deformed Maps
Akira Arahata, Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
pp. 43 - 48
DC2008-36
Scan-based Attack for an AES-LSI included with other IPs
Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ)
pp. 49 - 53
DC2008-37
Dynamically Variable Secure Scan Architecture against Scan-based Side Channel Attack on Cryptography LSIs
Hiroshi Atobe, Ryuta Nara, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
pp. 55 - 59
DC2008-38
A Power Masking Method of AES Circuit By Using Cross Bar Switch To Switch S-Box Circuit.
Nobuyuki Kawahata, Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ)
pp. 61 - 66
DC2008-39
On Handling Cell Placement with Exclusive Adjacent Symmetry Constraints for Analog IC Layout Design
Shimpei Asano, Kunihiro Fujiyoshi (Tokyo University of Agriculture and Technology)
pp. 67 - 72
DC2008-40
CAFE router: A Fast Connectivity Aware Multi-net Routing Algorithm for Routing Grid with Obstacles
Yukihide Kohira, Atsushi Takahashi (Tokyo Tech)
pp. 73 - 78
DC2008-41
Coarse-Grained Reconfigurable Architecture with Flexible Reliability
Younghun Ko, Dawood Alnajjar, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye (Osaka Univ.)
pp. 79 - 84
DC2008-42
Insertion-Point Selection of Canary FF for Timing Error Prediction
Yuji Kunitake (Kyushu Univ.), Toshinori Sato (Fukuoka Univ.), Seiichiro Yamaguchi, Hiroto Yasuura (Kyushu Univ.)
pp. 85 - 89
DC2008-43
Evaluating the reliability of Highly Reliable Cell Circuits
Keiichi Hotta, Takashi Nakada, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima (Nara Institute of Science and Technology)
pp. 91 - 96
DC2008-44
A Two-level Cache and Scratch Pad Memory Simulation for Embedded Systems
Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
pp. 97 - 102
DC2008-45
Evaluation of Hardware Algorithms on a Circuit Model Considering Wire Delay
Tetsuya Nagase, Kazuyoshi Takagi, Naofumi Takagi (Nagoya Univ.)
pp. 103 - 108
DC2008-46
Improving the Accuracy of Rule-based Equivalence Checking of High-level Desciptions by Identifying Potential Internal Equivalences
Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo)
pp. 109 - 114
DC2008-47
Generation of High Coverage Property Set Using Counterexamples
Takeshi Matsumoto, Yeonbok Lee, Hiroaki Yoshida (Univ. of Tokyo), Hisashi Yomiya (Toshiba Corporation), Masahiro Fujita (Univ. of Tokyo)
pp. 115 - 120
DC2008-48
[Poster Presentation]
A Test Point Insertion Method for Test Data Reduction Based on Necessary Assignment
Kazuko Hiramoto, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ)
pp. 121 - 126
DC2008-49
[Poster Presentation]
A Hybrid Delay Scan forDelay Testing Based on Propagation Dominance
Tomomi Nuwa, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
pp. 127 - 132
DC2008-50
A Reconfigurable Wrapper Design for Testing Cores with Multi-Clock Domains
Takashi Yoshida, Tomokazu Yoneda, Hideo Fujiwara (Nara Institute of Science and Technology)
pp. 133 - 138
DC2008-51
Variable Scheduling and Binding for High-Level Synthesis Considering Indefinite Cycle Operations
Yuki Toda, Nagisa Ishiura, Kousuke Sone (Kwansei Gakuin Univ.)
pp. 139 - 144
DC2008-52
A Multiplexer Reducing Algorithm in Floorplan-Aware High-level Synthesis for Distributed-Register Architectures
Tetsuya Endo, Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ)
pp. 145 - 150
DC2008-53
Delay Variability-Aware Datapath Synthesis Based on Safe Clocking for Setup and Hold Timing Constraints
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki (Japan Advanced Institute of Science and Technology)
pp. 151 - 156
DC2008-54
Enlarging The Solution Spaces For Schedulability Based On Skew Optimization
Takayuki Obata, Mineo Kaneko (Japan Advanced Institute of Science and Technology)
pp. 157 - 162
DC2008-55
Accuracy and Speed Improvement of Random Walk Simulation Using Walk Sharing and Return-to-Start Transient Analysis Technique
Hitoshi Miwa, Goro Suzuki (Univ. of Kitakyushu)
pp. 163 - 170
DC2008-56
Delay analysis method using stochastic process
Kazuki Hori, Goro Suzuki (Univ. of Kitakyushu)
pp. 171 - 175
DC2008-57
Power Noise Analysis Acceleration Technique by Linear Programming Method
Takeshi Gomakubo, Goro Suzuki (The Univ. of Kitakyushu)
pp. 177 - 182
DC2008-58
Leakage Power Reduction Method for Dual-Rail Four-Phase Asynchronous Circuits Using Multi-Vth Transistors
Koei Takada, Masashi Imai, Hiroshi Nakamura, Takashi Nanya (U. of Tokyo)
pp. 183 - 188
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.