IEICE Technical Report

Print edition: ISSN 0913-5685      Online edition: ISSN 2432-6380

Volume 107, Number 295

VLSI Design Technologies

Workshop Date : 2007-10-30 / Issue Date : 2007-10-23

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Table of contents

VLD2007-50
Simulation on the electric conduction of semiconductor with arrayed dopant
Tomohide Terunuma, Takanobu Watanabe (Waseda Univ.), Takahiro Shinada (ASMeW), Yoshinari Kamakura, Kenji Taniguchi (Osaka Univ.), Iwao Ohdomari (Waseda Univ.)
pp. 1 - 4

VLD2007-51
Comparative Study on Drive Current of non-Si n-Channel MOSFETs based on Quantum-Corrected Monte Calro Simulation
Takashi Mori, Yuusuke Azuma, Hideaki Tsuchiya (Kobe Univ.)
pp. 5 - 10

VLD2007-52
Coarse-grain quantum transport simulation of ultra-small MOSFETs
Gennady Mil'nikov, Nobuya Mori, Yoshinari Kamakura (Osaka Univ.), Tatsuya Ezaki (Hiroshima Univ.)
pp. 11 - 14

VLD2007-53
Crystalline Orientation effects on device characteristics in ultra-small multi-gate devices
Hideki Minari, Daisuke Nishitani, Nobuya Mori (Osaka Univ.)
pp. 15 - 18

VLD2007-54
[Invited Talk] Simulation technology for power devices
Ichiro Omura (Toshiba)
pp. 19 - 22

VLD2007-55
Electro-Thermal Compact Model for Reset Operation of Phase Change Memories
Atsushi Sakai, Kenichiro Sonoda, Masahiro Moniwa, Kiyoshi Ishikawa, Osamu Tsuchiya, Yasuo Inoue (Renesas Technology Corp.)
pp. 23 - 26

VLD2007-56
Study of Parasitic Resistance Behavior and Its Extraction Method on Deeply Scaled MOSFETs
Hideji Tsujii, Akira Hokazono, Makoto Fujiwara, Shigeru Kawanaka, Atsushi Azuma, Nobutoshi Aoki, Yoshiaki Toyoshima (Toshiba)
pp. 27 - 32

VLD2007-57
Impact of Shear Strain and Quantum Confinement on <110> Channel nMOSFET with High-Stress CESL
Hiroyuki Takashino, Takeshi Okagaki, Tetsuya Uchida, Takashi Hayashi, Motoaki Tanizawa, Eiji Tsukuda, Katsumi Eikyu, Shoji Wakahara, Kiyoshi Ishikawa, Osamu Tsuchiya, Yasuo Inoue (Renesas Technology Corp.)
pp. 33 - 36

VLD2007-58
Analysis of strain-dependent hole transport characteristics in bulk Ge-pMOSFETs
Hiroshi Takeda (NEC), Takeo Ikezawa, Michihito Kawada (NIS), Masami Hane (NEC)
pp. 37 - 41

VLD2007-59
Validation of the Effect of Full Stress Tensor in HoleTransport in Strained 65nm-node pMOSFETs
Eiji Tsukuda (Renesas), Yoshinari Kamakura (Osaka Univ.), Hiroyuki Takashino, Takeshi Okagaki, Tetsuya Uchida, Takashi Hayashi, Motoaki Tanizawa, Katsumi Eikyu, Shoji Wakahara, Kiyoshi Ishikawa, Osamu Tsuchiya, Yasuo Inoue (Renesas), Kenji Taniguchi (Osaka Univ.)
pp. 43 - 46

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan