IEICE Technical Report

Print edition: ISSN 0913-5685

Circuits and Systems

Workshop Date : 2007-01-30 / Issue Date : 2007-01-23

CAS2006-70
Experiment-based Evaluation of Algorithm Performance for the 2- or 3-Vertex Connectivity Augmentation Problem
Hiroharu Sumiyoshi, Daisuke Takafuji, Satoshi Taoka, Toshimasa Watanabe (Hiroshima Univ.)
pp. 1 - 6

CAS2006-71
Improvement of track layout of bipartite graph subdivisions
Miki Miyauchi (NTT)
pp. 7 - 12

CAS2006-72
A Circuit Partitioning Algorithm for Multi-FPGA Systems with Time-multiplexed I/Os
Masato Inagi, Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC)
pp. 13 - 17

CAS2006-73
Remote hwObject hardware structure of hw/sw complex
Hiroaki Iijima, Hiroshi Kishimoto, Masatoshi Sekine (tuat)
pp. 19 - 24

CAS2006-74
Multilevel control circuit of hwObject for servo control system
Hiroaki Maekawa, Hiroaki Iijima, Masatoshi Sekine (TUAT)
pp. 25 - 30

CAS2006-75
Computational Complexity of Simultaneous Optimization of Skew, Schedule and Clock in High-Level Synthesis
Takayuki Obata, Mineo Kaneko (JAIST)
pp. 31 - 36

CAS2006-76
A Test Generation Framework using Checker Circuits and its Application to Path Delay Test Generation
Tsuyoshi Iwagaki (JAIST), Satoshi Ohtake (NAIST), Mineo Kaneko (JAIST), Hideo Fujiwara (NAIST)
pp. 37 - 42

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan