1月16日開催　講演会のお知らせ

日　時：2024年1月16日（火）13:30〜14:30
会　場：高知工科大学香美キャンパス　教育研究棟A103
題　目：Introduction to Analysis and Debugging of Transient Faults
講　師：National Tsing Hua University, Department of Electrical Engineering
Professor Jing-Jia Liou
概　要：Transient fault is an error model that flips a register or memory bit at certain cycles of a digital circuit, e.g, a processor core. The model is commonly applied in evaluating the reliability of a digital system including both software and hardware. For example, we may inject sampled transient faults and run a software to observe the hardware faulty behavior, so error outputs can be analyzed and mitigated. On the other hand, when a system captures and shows error symptom during validation, a debugging process will often start with tracing the root cause to a certain transient fault and then follow up with failure analysis. For both above applications, we face the issue that the number of transient faults is simply too large for a full comprehensive analysis. In this talk, we will introduce and discuss methods on how to analyze and reduce the number of transient faults. In our experiments with two RISC-V cores, only under 1-3% of faults remains necessary for processing, which can drastically improve our reliability analysis for a digital system.