Summary
International Symposium on Antennas and Propagation
2010
Session Number:4FD1
Session:
Number:4FD1-3
On Chip Transformer Design for CMOS Power Amplifiers
Hyeonseok Hwang, Moonsuk Jung, Byeonghak Jo, Gyuseok Kim, Sugyeong Kim, Hyun Paek, Yoosam Na,
pp.-
Publication Date:2010/11/23
Online ISSN:2188-5079
Summary:
CMOS technology has been widely applied to the design of RF circuits by advantage of low cost, compact size and high system-on-chip integration capability. But the high power amplifier is undesirable building block for C MOS process due to the low breakdown voltage of gate oxide[1]. This problem becomes more serious as the minimum gate lengths are scaled down in each new process generation. The other problem associated with the design of on-chip power amplifiers using CMOS processes is the high loss of on-chip impedance transformation [2]. This is caused by the highly conductive substrate, as well as thin metal and dielectric layers. Recently, many literatures have been presented CMOS power amplifiers in wireless communications comparable to other process ones. The breakdown voltage is one of the inherited drawbacks of CMOS transistor, so typical CMOS power amplifiers adapted the cascode type differential structure as in figure 1 to relieve the voltage stress at the output. Due to the limitation of the output voltage swing, the optimum load for the power cell should be minimized. Also, its structure inevitably needs differential to single-ended conversion at output stage[3]. In this work, we proposed on chip transformer targeted to around 900 MHz WCDMA application. At these frequencies, small size and low loss impedance transformation is challengeable task. The transformer was fabricated by standard 0.18 μm RF CMOS process which support two thickest top metals.