Summary
International Symposium on Electromagnetic Compatibility
2009
Session Number:22Q2
Session:
Number:22Q2-2
A Study on Prediction of Parallel Impedance of Closely Mounted Bypass Capacitors
H. Yamamoto,
pp.345-348
Publication Date:2009/7/20
Online ISSN:2188-5079
Summary:
In this paper, the effective layout of decoupling capacitors is discussed. As a high-speed digital IC, to minimize the power supply impedance is one of the important issues to control voltage fluctuations and to prevent an electromagnetic noise. And many bypass capacitors are used in the very crowded space to decrease impedance of power supply circuit. However, to estimate parallel impedance of these capacitors is difficult because of influence of magnetic coupling. Here, a simple model to estimate the mutual inductance between two bypass capacitors is proposed. By using this model, an easy, more accurate impedance prediction of the parallel, closely mounted capacitors became possible. The impedance when the capacitors were used in several typical layouts was calculated by this method. The results ware verified by the measurement. Also, effective layout to decrease impedance was discussed. This technique was also applied to 3-terminal capacitor.