Summary

Proceedings of the 2013 International Symposium on Nonlinear Theory and its Applications

2013

Session Number:C4L-D

Session:

Number:507

Asynchronous Digital Circuit Design using Noise-Driven Stochastic Gates

Gonzalez-Carabarin Lizeth,  Tetsuya Asai,  Masato Motomura,  

pp.507-510

Publication Date:

Online ISSN:2188-5079

DOI:10.15248/proc.2.507

PDF download (574.9KB)

Summary:
This paper presents a novel CMOS configuration of the basic logic gates using the concept of stochastic resonance (SR). In this framework, the SR effect applied to nonlinear electrical systems to build logical gates (SR gates) have been studied. These systems exhibit hysteresis; this property is crucial, because it ensures the stability of all logic states. Moreover, the application of an external bias, allows the selection of logic operation. However, in this configuration the timing is limited, which has been reviewed in this study; therefore, the most suitable applications of the SR gates are in asynchronous circuit design. The Huffman model is used to simulate the performance of a sequential circuit, designed with the SR gates. SPICE simulations are run using a 0.18-μm CMOS technology. The simulations results have proven the effective performance of the SR gates for an optimal amount of noise, despite the introduction of an intentional mismatch between the threshold voltages of the transistors.

References:

[1] L. Gammaitoni, P. Hanggi, P. Jung, F. Marchesoni, ”Stochastic resonance,” Rev. Mod. Phys., vol. 70, pp. 223-287, 1998.

[2] P. Hanggi, ”Stochastic resonance in biology - How noise can enhance detection of weak signals and help improve biological information processing,” Chem. Phys. Chem. vol. 3, pp. 285, 2002.

[3] K. Murali, S. Sinha, W.L. Ditto, A.L. Bulsara, ”Reliable logic circuits that exploit nonlinearity in the presence of a Noise Floor,” Phys. Rev. Lett., vol. 102, pp. 104101, 2009.

[4] A. R. Bulsara, A. Dari, W. L. Ditto, K. Murali, and S. Sinha, ”Logical stochastic resonance,” Chemical Physics, vol. 375 pp. 424-434, Jun. 2010.

[5] C. Mayer, ”Asynchronous circuit Design”, John Wiley and Sons, 2001.