Summary
International Symposium on Nonlinear Theory and its Applications
2009
Session Number:C3L-C
Session:
Number:C3L-C2
A Clock-Period Comparison ADPLL with a Linearity Improved DCO
Yukinobu Makihara, Masayuki Ikebe, Junichi Motohisa, Eiichi Sano,
pp.-
Publication Date:2009/10/18
Online ISSN:2188-5079
Summary:
We proposed new architecture of phase-locked loop (PLL) by using clock-period comparison. For a digitally controlled PLL, we evaluated the use of a clock-period comparator (CPC). In proposed PLL, only the frequency lock operation should be performed; however, the frequency control by CPC results in the phase lock operation. Thus, the phase lock operation is also simultaneously achieved. We designed element blocks of the proposed PLL using a 0.25-μm CMOS process. We succeeded in digitizing a voltage controlled oscillator (VCO) with a linear characteristic. We also confirmed a phase lock operation by measurement.