Summary
International Symposium on Nonlinear Theory and its Applications
2008
Session Number:B4L-D
Session:
Number:B4L-D1
Application of Latency Insertion Method to CMOS Circuit Simulation
Tadatoshi Sekine, Hideki Asai,
pp.-
Publication Date:2008/9/7
Online ISSN:2188-5079
Summary:
This paper describes one of the accurate application techniques of Latency Insertion Method to a CMOS circuit simulation. First, the update equations of a CMOS inverter are formulated for 3 regions. Then, we discuss the accuracy of the proposed technique and the existing one with some actual numerical results. Finally, it is confirmed that the proposed technique enables more accurate and faster simulation of a CMOS inverter chain circuit than an existing one.