Summary
International Symposium on Nonlinear Theory and its Applications
2010
Session Number:A2L-B
Session:
Number:A2L-B3
Mapping of High Performance Data-flow Graphs into Programmable Logic Devices
Csaba Nemes, Zoltan Nagy, Miklos Ruszinko, Andras Kiss, Peter Szolgay,
pp.99-102
Publication Date:2010/9/5
Online ISSN:2188-5079
Summary:
In high-performance processors computation time and communication delay are comparable. Only those design methodologies can be successful which take care of the precedence of locality. In this article new design methodology is introduced which partitions the execution units and assigns a locally distributed control unit to each partition. Execution and control are relatively fast inside the partition and this results in a speed gain contrast to the global control unit where the fan out of the wiring can cause a slow operation. An optimization problem is described and an algorithm is developed which targets to find the optimal partitioning where fast local control units can be used with relatively small area increase. The optimal solution of the partitioning problem is NP complete [1] but a reasonable algorithm can be constructed for practical engineering applications. We have successfully designed a greedy algorithm and tested on few test cases.