Summary
2007 International Symposium on Nonlinear Theory and its Applications
2007
Session Number:17PM2-A
Session:
Number:17PM2-A-4
A Circuit Design for Compact Sigma-Delta Domain Multiplier
Tsubasa Katao, Keita Hayashi, Hisato Fujisaka, Takeshi Kamio, Kazuhisa Haeiwa,
pp.63-66
Publication Date:2007/9/16
Online ISSN:2188-5079
DOI:10.34385/proc.41.17PM2-A-4
Summary:
In this paper we consider reducing logic gates used to build Sigma-Delta (SD) domain multipliers. The reduction brings not only compactness and low cost to every SD domain processors but also high precision even to middle scale processors. In inherently noisy SD domain, it is very important to attain highly precise multiplication. Ordinary multiplication procedure in SD domain is summation of sub-products. There exist integers that products of two integers ∈{1, 2, ・ ・ ・ , k} never take in {1, 2, ・ ・ ・ , k2}. By decreasing the redundancy, it is possible to design SD domain multipliers with small adders for summing sub-products. The designed multipliers can be built of about a half of logic gates required to build the preceding multipliers.