Summary
2007 International Symposium on Nonlinear Theory and its Applications
2007
Session Number:17PM1-A
Session:
Number:17PM1-A-1
An Ultra Low-Power High-Speed Rail-to-Rail Buffer Amplifier for LCD Source Drivers
Jun PAN, Zheng LIANG, Wei-Lun HUANG, Yasuaki INOUE,
pp.3-6
Publication Date:2007/9/16
Online ISSN:2188-5079
DOI:10.34385/proc.41.17PM1-A-1
Summary:
An ultra low-power high-speed rail-to-rail buffer amplifier with improved current summing circuit is proposed for LCD source drivers. By placing two complementary differential pairs in parallel, it is possible to obtain a rail-to-rail input stage. Then, a current summing circuit with two embedded comparators is proposed. With the proposed current summing circuit, the output stages will be turned off at static state to reduce quiescent current, while keeping large driving capacity when they are turned on at dynamic state. In addition, the proposed buffer amplifier will not increase the chip size so that the buffer amplifier can be made compact. Simulation with a 0.35 μm CMOS technology demonstrates that the buffer has a quiescent current of 2.0 μA and a maximum tracking error of 0.16 LSB with 100% rail-to-rail input swing. Settling time of 1.5 μs and 2.1 μs for the rising and falling edge is measured for rail-to-rail voltage swing with 600 pF capacitance load, which is sufficient for driving large LCD panels.