Summary
International Technical Conference on Circuits/Systems, Computers and Communications
2016
Session Number:P3
Session:
Number:P3-9
A Cache Design to Optimize Memory Performance in Mobile Proceesor
Su In Kim, Chang Min Eun, Hyun Hak Cho, Ok Hyun Jeong ,
pp.1025-1028
Publication Date:2016/7/10
Online ISSN:2188-5079
Summary:
In recent years, the processor performance has been improved rapidly, but the enhancement speed of memory performance is slow. Due to this gap, the improvement of memory performance is significant, and enhancing the cache performance can assist that. For this reason, we designed the cache that optimizes memory performance in the target processor, Cortex-A57. To evaluate memory and processor performance, Average Memory Access Time (AMAT) and Cycles Per Instruction (CPI) were used, and the simulation was conducted by using SimpleScalar3.0 and benchmarks from SPEC CPU2000. As a result, the performance was enhanced by 34.93% in AMAT and 10.05% in CPI with proposed design which is optimized to target processor. It is contributed to performance improvement of mobile processor as well.