Summary
International Technical Conference on Circuits/Systems, Computers and Communications
2016
Session Number:P2
Session:
Number:P2-7
A Space-Efficient Footprint DRAM Cache
Jongwon Kim, Yongjun Lee, Hakbeom Jang, Jae W. Lee ,
pp.941-942
Publication Date:2016/7/10
Online ISSN:2188-5079
Summary:
Recently, 3D die-stacked DRAM technologies have been adopted by many processor vendors as a solution to the memory wall problem. To effectively utilize this large in-package memory, there are proposals to use it as a cache. Page-based caches have drawn much attention to reduce the cost of tags by increasing the granularity of caching. However, page-based caches waste cache capacity by over-fetching blocks that are not actually used during the page's lifetime in the DRAM cache. In this paper, we introduce a novel footprint caching technique, which greatly improves the space efficiency of a page-based cache. The key idea is to overlay two sparse pages with many invalide blocks into a single physical page, thus maximizing page utilization. Our cache design improves the IPC by 17.9% and reduces cache miss by 5% over a state-of-the-art footprint cache.