Summary
International Technical Conference on Circuits/Systems, Computers and Communications
2016
Session Number:P2
Session:
Number:P2-3
MILP-based Scheduling for Clock Latency Minimization in High-level Synthesis
Keisuke Inoue, Mineo Kaneko ,
pp.925-928
Publication Date:2016/7/10
Online ISSN:2188-5079
Summary:
The hardware cost of the realization of a clock skew schedule tends to increase due to additional delay elements. Therefore, there is a demand to reduce clock latencies at early design stage. This paper discusses a novel design problem in high-level synthesis, to minimize clock latencies with scheduling, since scheduling highly affects the required clock latencies. Experimental results show that the proposed approach can reduce, the maximum clock latency, and the sum of clock latencies, over the conventional design.