Summary
International Technical Conference on Circuits/Systems, Computers and Communications
2016
Session Number:P1
Session:
Number:P1-5
A Design of a Low Noise and Low Power Low Drop Out Regulator with Fast Settling Time Technique
Jung-Yeon Kim, Seong-Jin Oh, Dong-Soo Lee, Kang-Yoon Lee ,
pp.851-852
Publication Date:2016/7/10
Online ISSN:2188-5079
Summary:
This Paper presents a low noise and low power Low Drop Out regulator (LDO) with fast settling time technique. Using Low Pass Filter (LPF) at the output of Band Gap Reference (BGR) and using output shunt capacitor at the output of LDO are the most efficient ways of suppressing output noise. Its settling time, however, is extremely slow because of large resistance and capacitance. By adopting the proposed fast settling time technique, settling time becomes 6 times faster compared to the normal situation while maintaining outstanding output noise characteristics. This circuit is designed in CMOS 55 nm process and the output noises are 300 nV⁄√Hz, 22 nV⁄√Hz, and 0.21 nV⁄√Hz at 10 kHz, 100 kHz, and 1 MHz, respectively. Settling time of LDO is 150 us and the output of the proposed LDO is 850 mV. The current consumption including BGR and LDO is 82 uA when the supply voltage is 1.2 V