Summary
International Technical Conference on Circuits/Systems, Computers and Communications
2016
Session Number:M3-6
Session:
Number:M3-6-3
Compact and High-Speed Hardware Feature Extraction Accelerator for Dense Scale-Invariant Feature Transform
Tetsushi Koide, Takumi Okamoto, Tatsuya Shimizu, Koki Sugi, Anh-Tuan Hoang, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Shigeto Yoshida, Hiroshi Mieno, Shinji Tanaka ,
pp.387-390
Publication Date:2016/7/10
Online ISSN:2188-5079
Summary:
This paper presents a D-SIFT based feature extraction hardware accelarator in real-time computer-aided diagnosis (CAD) system for endoscopic images. From an FPGA implimentation, we have demonstrated the proposed hardware oriented D-SIFT architecture was very compact due to no multipication and was very suitable for stream based image processing. The processing speed for Full-HD (1920x1080) high resoltion image is only 20 msec@100 MHz and it is about 700 times faster than that of software implimentation (14 sec) within low latency. The proposed D-SIFT accelarator can be also applicable for the feature exstruction part for various types of image processing including 4 K and 8 K high resolusion images.