Summary
International Technical Conference on Circuits/Systems, Computers and Communications
2016
Session Number:M2-4
Session:
Number:M2-4-5
An Efficient Hardware Architecture for Calculating the Minimum SAD with Parallel Execution at the Search Point Level
Tae Sung Kim, Hyuk-Jae Lee, Chae Eun Rhee ,
pp.193-196
Publication Date:2016/7/10
Online ISSN:2188-5079
Summary:
Integer Motion Estimation (IME) is one of the key components of video coding standard such as high-efficiency video coding (HEVC). As HEVC adopts a highly flexible block partitioning structure from 4x4 to 64x64, performing IME for every block partition demands considerable computational complexity. Although a number of previous works for efficient hardware architectures to accerarate IME have been done, the computational complexity of IME keeps growing as the video resolution increases. In this paper, an efficient hardware architecture for calculating the minimum SAD is proposed. The proposed hardware exploits the parallelism of multiple search points. To improve the efficiency of the proposed hardware, SAD calculation and its comparison steps are performed in a pipelined manner and the workload between the two pipeline stages are finely balanced. The proposed hardware processes 32 search points for an 8x8 block. The gate count is 827 K and the maximum operating clock frequency is 485.44 MHz.