Summary
International Technical Conference on Circuits/Systems, Computers and Communications
2016
Session Number:M2-2
Session:
Number:M2-2-4
Comparative Analysis on Replica Techniques for Bit-Line Tracking in 14-nm node
Se-Hyeok Oh, Han-Wool Jeong, Seong-Ook Jung ,
pp.151-154
Publication Date:2016/7/10
Online ISSN:2188-5079
Summary:
Replica bit-line technique is used for generating sense amplifier enable signal which accurately tracks bit-line delay of SRAM. However, threshold voltage variation in the replica bit-line circuit changes the cell current, which results in variation of the sense amplifier enable time, TSAE. The variation of TSAE makes the sensing operation unstable. In this paper, in addition to conventional replica bit-line delay (RBLconv), dual replica bit-line delay (DRBD) and multi-stage dual replica bit-line delay (MDRBD) which are used for reducing TSAE variation are briefly introduced, and the maximum possible number of on-cell which can satisfy 6σ sensing yield is determined through simulation at a supply voltage of 0.6 V with 14 nm FinFET technology. As a result, it is observed that delay of DRBD and MDRBD are respectively improved by 24.4% and 48.3% compared with that of RBLconv and energy consumptions are respectively reduced by 8% and 32.4% compared with that of RBLconv.