Deadline-Constrained Static Mapping of Parallelizable Tasks on Manycore Architectures

Yining Xu; Ittetsu Taniguchi; Hiroyuki Tomiyama

Summary

International Technical Conference on Circuits/Systems, Computers and Communications

2016

Session Number:M1-2

Session:

Number:M1-2-1

Deadline-Constrained Static Mapping of Parallelizable Tasks on Manycore Architectures

Yining Xu, Ittetsu Taniguchi, Hiroyuki Tomiyama ,

pp.33-36

Publication Date:2016/7/10

Online ISSN:2188-5079

DOI:10.34385/proc.61.M1-2-1

PDF download (887.5KB)

Summary:

This paper proposes a static task mapping technique for manycore architectures. The technique tries to minimize the number of cores while satisfying deadline constraints of individual tasks.