Summary
Asia-Pacific Conference on Communications
2008
Session Number:15-PM1-C
Session:
Number:1569126829
Fast Link-Disjoint Path Algorithm on Parallel Reconfigurable Processor DAPDNA-2
Taku KIHARA, Sho SHIMIZU, Yutaka ARAKAWA, Naoaki YAMANAKA, Kosuke SHIBA,
pp.-
Publication Date:2008/10/14
Online ISSN:2188-5079
DOI:10.34385/proc.27.1569126829
Summary:
This paper proposes fast parallel link-disjoint path algorithm using dynamically reconfigurable processor and implements it on DAPDNA-2 (IPFlex Inc) which is newly structured. The conventional k-shortest path algorithm finds multiple link-disjoint paths between the source node and the destination node. When the network scale is large, the calculation time of k-shortest path algorithm increases rapidly. Moreover, in the worst case, k-shortest path algorithm can not find optimum link-disjoint path pair because this algorithm always finds the shortest path at first and removes those links from network. Our proposed algorithm collects all path information in the network and calculates optimum link-disjoint path pair (i.e. minimum cost link-disjoint path pair) at high speed by using parallel operation. Additionally, our proposed algorithm finds optimum link-disjoint path pair at a high rate in a limited of calculation time. The evaluation shows our proposed algorithm can decrease the calculation clock about 90%.