Summary
Asia-Pacific Conference on Communications
2008
Session Number:15-AM2-C
Session:
Number:1569121993
A Monolithic 10-Gb/s CMOS Limiting Amplifier for Low Cost Optical Communication Systems
Bangli Liang, Tad Kwasniewski, Zhigong Wang, Dianyong Chen, Bo Wang, Dezhong Cheng,
pp.-
Publication Date:2008/10/14
Online ISSN:2188-5079
DOI:10.34385/proc.27.1569121993
Summary:
In this paper, a 10-Gb/s limiting amplifier (LA) was implemented in 0.18μm CMOS. Modified active inductors and active feedback topology are employed to eliminate the trade-off among circuit bandwidth, power dissipation, and layout area, which is suitable for low cost applications. Based on the measurement results, the realized LA can operate up to 12-Gb/s with a 125mVpp single-ended output through equivalent 25-Ω load. The input dynamic range is 40dB corresponding to the signal level range from 4mV to 400mV. The RMS jitter of the output signal is 2ps and the total power dissipation (including output buffer) is only 60mW under a supply of 1.8V.