number | title/author |
---|---|
2A2-1 | Using cavity-modes for modeling of via-connected power bus stacks in multilayer PCBs Z.L. Wang, O. Wada, T. Yaguchi, |
2A2-2 | Investigation of capacitor allocation to reduce EMI arising from a via-hole penetrating through power-distribution planes T. Harada, N. Kobayashi, T. Yaguchi, |
2A2-3 | Experimental evaluation of a low EMI multilayer PCB structure for high speed digital circuit D. Iguchi, |
2A2-4 | A generation mechanism of electromagnetic noise on the circuit due to ground potential variation A. Mutoh, S. Nitta, |