Presentation	2015-03-03 A Virtual/Real Combined Verification Method for FPGAs Yoshimasa ISHINO,
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Abstract(in English)	The biggest advantage of FPGA is that can change the circuits at any time. Therefore, verification in virtual stage becomes neglected, and has led to prolonged verification in real stage. FPGA verification using only exhaustive simulation for ASIC, eliminate the advantages of the FPGA. In this paper, we introduce a method that combines the virtual and real stage verification to reduce the development period. Virtual verification using SystemC detects the defects of design at an earlier stage. Real verification using the FPGA standard on-chip IPs reduces the system verification period. This development process realizes 40% reduction of FPGA development period compared with conventional verification methods.
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Keyword(in English)	SystemC / FPGA / Quantitative Project Management / High-Level Synthesis
Paper #	VLD2014-167
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Conference Information
Committee	VLD
Conference Date	2015/2/23(1days)
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Paper Information
Registration To	VLSI Design Technologies (VLD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	A Virtual/Real Combined Verification Method for FPGAs
Sub Title (in English)
Keyword(1)	SystemC
Keyword(2)	FPGA
Keyword(3)	Quantitative Project Management
Keyword(4)	High-Level Synthesis
1st Author's Name	Yoshimasa ISHINO
1st Author's Affiliation	Mitsubishi Electric Micro-Computer Application Software Co.,Ltd.()
Date	2015-03-03
Paper #	VLD2014-167
Volume (vol)	vol.114
Number (no)	476
Page	pp.pp.-
#Pages	5
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