| Presentation | 2015-03-03 Generation of Asynchronous Circuits from a High-level Synthesis Tool Taichi KOMINE, Hiroshi SAITO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we propose a method which converts an RTL model generated by a high-level synthesis tool to asynchronous circuits with bundled-data implementation. The proposed method uses an internal information of the high-level synthesis tool to generate an asynchronous control circuit. Then, clock signals for registers are replaced with acknowledge signals from the asynchronous control circuit. The proposed method also generates a set of design constraints and a script for logic synthesis, and a Makefile for Register Transfer Level (RTL) simulation. In experiments, we confirmed the behaviors of generated asynchronous RTL models with the evaluation in terms of area ad latency. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Asynchronous circuits with bundled-data implementation / high-level synthesis / generation of asynchronous circuits / constraint generation |
| Paper # | VLD2014-165 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2015/2/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Generation of Asynchronous Circuits from a High-level Synthesis Tool |
| Sub Title (in English) | |
| Keyword(1) | Asynchronous circuits with bundled-data implementation |
| Keyword(2) | high-level synthesis |
| Keyword(3) | generation of asynchronous circuits |
| Keyword(4) | constraint generation |
| 1st Author's Name | Taichi KOMINE |
| 1st Author's Affiliation | Graduate School of Computer Science and Enginnering, University of Aizu() |
| 2nd Author's Name | Hiroshi SAITO |
| 2nd Author's Affiliation | Graduate School of Computer Science and Enginnering, University of Aizu |
| Date | 2015-03-03 |
| Paper # | VLD2014-165 |
| Volume (vol) | vol.114 |
| Number (no) | 476 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |