Presentation 2015-03-03
ILP Based Synthesis for Area-Efficient Soft-Error Tolerant Datapaths
Junghoon OH, Mineo KANEKO,
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Abstract(in English) As the device size decreases, reliability degradation caused by soft-errors has become one of the greatest issues in VLSIs. In our previous study, we proposed a method to synthesize soft-error tolerant application-specific datapaths via high-level synthesis. Our method is based on a concurrent error detection and a retry mechanism for error detection and correction, and adopts speculative resource sharing between retry parts and secondary parts for hardware/time overhead mitigation. In this paper, we propose an integer linear programming-based solution for area-efficient soft-error tolerant datapath synthesis considering speculative resource sharing.
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Keyword(in English) integer linear programming / speculative resource sharing / redundancy / soft-error / high-level synthesis
Paper # VLD2014-164
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Conference Information
Committee VLD
Conference Date 2015/2/23(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) ILP Based Synthesis for Area-Efficient Soft-Error Tolerant Datapaths
Sub Title (in English)
Keyword(1) integer linear programming
Keyword(2) speculative resource sharing
Keyword(3) redundancy
Keyword(4) soft-error
Keyword(5) high-level synthesis
1st Author's Name Junghoon OH
1st Author's Affiliation School of Information Science, Japan Advanced Institute of Science and Technology()
2nd Author's Name Mineo KANEKO
2nd Author's Affiliation School of Information Science, Japan Advanced Institute of Science and Technology
Date 2015-03-03
Paper # VLD2014-164
Volume (vol) vol.114
Number (no) 476
Page pp.pp.-
#Pages 6
Date of Issue