| Presentation | 2015-03-03 Methodology for Reduction of Timing Margin by Considering Correlation between Process Variation and BTI Michitarou YABUUCHI, Kazutoshi KOBAYASHI, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We analyze the efficiency of the design methodology by using circuit simulations. The design methodology which considers the correlation between process variations and BTI (Bias Temperature Instability)-induced degradations reduces timing margins of circuits without threatening their reliability. Because the reliability issues become significant problems in the heavily scaled process, circuit designers should consider them. The reliable design methodology for high performance circuits is required. There is the correlation between process variations and BTI-induced degradations. The degradation rates of MOSFETs which have low initial threshold voltages are lower than the other variation conditions. We propose the design methodology which considering the correlation and analyze its efficiency for circuit designs. We confirm the timing margins are reduced by 10% with our methodology. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | BTI / process variation / reliability / degradation prediction |
| Paper # | VLD2014-163 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2015/2/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Methodology for Reduction of Timing Margin by Considering Correlation between Process Variation and BTI |
| Sub Title (in English) | |
| Keyword(1) | BTI |
| Keyword(2) | process variation |
| Keyword(3) | reliability |
| Keyword(4) | degradation prediction |
| 1st Author's Name | Michitarou YABUUCHI |
| 1st Author's Affiliation | Graduate School of Science and Technology, Kyoto Institute of Technology() |
| 2nd Author's Name | Kazutoshi KOBAYASHI |
| 2nd Author's Affiliation | Graduate School of Science and Technology, Kyoto Institute of Technology |
| Date | 2015-03-03 |
| Paper # | VLD2014-163 |
| Volume (vol) | vol.114 |
| Number (no) | 476 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |