| Presentation | 2015-03-03 A low-power soft error tolerant latch scheme Saki TAJIMA, Youhua SHI, Nozomu TOGAWA, Masao YANAGISAWA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In recent technology scaling, reduction of reliability by soft-error and increase power has appeared as an inevitable problem for logic circuits. We propose a low-power and high soft-error tolerant latch called TSPC-SEH latch based Soft Error Hardened (SEH) latch and True Single Phase Clock (TSPC). To compere SEH latch and DICE latch, the proposed latch archives 42% power reduction, and 54%s delay reduction. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Power / Radiation-Hard Redundant Latch / Dual Interlocked storage Cell (DICE) / Soft Error Hardened (SEH) Latch |
| Paper # | VLD2014-162 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2015/2/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A low-power soft error tolerant latch scheme |
| Sub Title (in English) | |
| Keyword(1) | Power |
| Keyword(2) | Radiation-Hard Redundant Latch |
| Keyword(3) | Dual Interlocked storage Cell (DICE) |
| Keyword(4) | Soft Error Hardened (SEH) Latch |
| 1st Author's Name | Saki TAJIMA |
| 1st Author's Affiliation | Waseda University() |
| 2nd Author's Name | Youhua SHI |
| 2nd Author's Affiliation | Waseda University |
| 3rd Author's Name | Nozomu TOGAWA |
| 3rd Author's Affiliation | Waseda University |
| 4th Author's Name | Masao YANAGISAWA |
| 4th Author's Affiliation | Waseda University |
| Date | 2015-03-03 |
| Paper # | VLD2014-162 |
| Volume (vol) | vol.114 |
| Number (no) | 476 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |