| Presentation | 2015-03-03 A Processor-Level NBTI Mitigation Technique of Applying Anti-Aging Gate Control through Instruction Set Architecture Song BIAN, Michihiro SHINTANI, Zheng WANG, Masayuki HIROMOTO, Anupam CHATTOPADHYAY, Takashi SATO, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | As the technology process of transistors becomes yet smaller, Negative Bias Temperature Instability (NBTI) has became one of the major threat to the performance and reliability of modern digital circuits. In this research, we propose a technique to mitigate the NBTI aging effect in processors by utilizing the NOP (No Operation) instruction to support a hardware-level modification. First, vectorless probability analysis is applied to each gate in the critical paths, and NBTI-stressed gates are identified. Second, specially-crafted gates are inserted to the upstream of stressed gates. Finally, the healing functionality of the inserted special gates are initiated by the NOP instruction, and the downstream gates are then healed. The proposed technique was applied to an example five-stage pipelined processor. Simulation results indicate that our method achieved about 12.5 % improvement in the worst-case path delay in a 10-year span with only a small amount of area and power overheads. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | vectorless probability analysis / NBTI mitigation / processor aging / reliability |
| Paper # | VLD2014-161 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2015/2/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Processor-Level NBTI Mitigation Technique of Applying Anti-Aging Gate Control through Instruction Set Architecture |
| Sub Title (in English) | |
| Keyword(1) | vectorless probability analysis |
| Keyword(2) | NBTI mitigation |
| Keyword(3) | processor aging |
| Keyword(4) | reliability |
| 1st Author's Name | Song BIAN |
| 1st Author's Affiliation | Graduate School of Informatics, Kyoto University() |
| 2nd Author's Name | Michihiro SHINTANI |
| 2nd Author's Affiliation | Graduate School of Informatics, Kyoto University |
| 3rd Author's Name | Zheng WANG |
| 3rd Author's Affiliation | RWTH Aachen University |
| 4th Author's Name | Masayuki HIROMOTO |
| 4th Author's Affiliation | Graduate School of Informatics, Kyoto University |
| 5th Author's Name | Anupam CHATTOPADHYAY |
| 5th Author's Affiliation | Nanyang Technological University |
| 6th Author's Name | Takashi SATO |
| 6th Author's Affiliation | Graduate School of Informatics, Kyoto University |
| Date | 2015-03-03 |
| Paper # | VLD2014-161 |
| Volume (vol) | vol.114 |
| Number (no) | 476 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |