| Presentation | 2015-03-02 Area Minimization of One-Dimensional Layout for MOS Circuits by SAT Solver and Simulated Annealing Hayato MASHIKO, Yukihide KOHIRA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In the design of one-dimensional layout for the circuits using MOSFETs such as dynamic CMOS circuits, the maximization of the number of shared diffusions has been focused on to minimize the layout area. However, the number of shared diffusions does not always correspond to the layout area in general. In our research, we focus on the circuits where the logic functions are realized by either nMOS or pMOS. To minimize the areas of these circuits, SAT solver and simulated annealing are applied to explore a best solution. We propose the formulation of the area minimization problem for one-dimensional layout to SAT problem. Furthermore, in simulated annealing, we propose a pertubation method which does not degrade the quality of obtained solution with high convergence compared to search in all solution space. In the experiments, the effectiveness of the proposed methods is confirmed. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | One-dimensional layout / diffusion sharing / track / SAT solver / simulated annealing |
| Paper # | VLD2014-158 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2015/2/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Area Minimization of One-Dimensional Layout for MOS Circuits by SAT Solver and Simulated Annealing |
| Sub Title (in English) | |
| Keyword(1) | One-dimensional layout |
| Keyword(2) | diffusion sharing |
| Keyword(3) | track |
| Keyword(4) | SAT solver |
| Keyword(5) | simulated annealing |
| 1st Author's Name | Hayato MASHIKO |
| 1st Author's Affiliation | School of Computer Science, the University of Aizu() |
| 2nd Author's Name | Yukihide KOHIRA |
| 2nd Author's Affiliation | School of Computer Science, the University of Aizu |
| Date | 2015-03-02 |
| Paper # | VLD2014-158 |
| Volume (vol) | vol.114 |
| Number (no) | 476 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |