Presentation 2015-02-19
The Development and Implementation of FPLL Technology for Satellite Communication
Hideki ISHIHARA, Toshiyuki UKEBA, Takashi OKAZAKI, Kyoichiro IZUMI, Ryuji ISHII,
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Abstract(in English) This paper describes the FPLL (Frequency & Phase Locked Loop) technology that we developed to reduce the scale of PSK-PM (Phase Shift Keying-Phase Modulation) demodulator circuit. PSK-PM is typically applied to the command channel for satellites. The FPLL technology reduces the circuit by means of implementing AFC (Automatic Frequency Control) and CR (Carrier Recovery) on an identical closed-loop circuit. The dual mode demodulator of PSK-FM (Phase Shift Keying-Frequency Modulation) and PSK-PM was realized in an FPGA for space by FPLL technology.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Telemetry Tracking & Communication / PSK-PM / FPLL / Frequency & Phase Locked Loop / AFC / PLL
Paper # SAT2014-68
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Committee SAT
Conference Date 2015/2/11(1days)
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Registration To Satellite Telecommunications (SAT)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) The Development and Implementation of FPLL Technology for Satellite Communication
Sub Title (in English)
Keyword(1) Telemetry Tracking & Communication
Keyword(2) PSK-PM
Keyword(3) FPLL
Keyword(4) Frequency & Phase Locked Loop
Keyword(5) AFC
Keyword(6) PLL
1st Author's Name Hideki ISHIHARA
1st Author's Affiliation MITSUBISHI ELECTRIC Corporation, Kamakura Works()
2nd Author's Name Toshiyuki UKEBA
2nd Author's Affiliation MITSUBISHI ELECTRIC Corporation, Kamakura Works
3rd Author's Name Takashi OKAZAKI
3rd Author's Affiliation MITSUBISHI ELECTRIC Corporation, Kamakura Works
4th Author's Name Kyoichiro IZUMI
4th Author's Affiliation MITSUBISHI ELECTRIC Corporation, Kamakura Works
5th Author's Name Ryuji ISHII
5th Author's Affiliation MITSUBISHI ELECTRIC Corporation, Kamakura Works
Date 2015-02-19
Paper # SAT2014-68
Volume (vol) vol.114
Number (no) 449
Page pp.pp.-
#Pages 5
Date of Issue