| Presentation | 2015-02-13 Note on Evaluation of Dependable Design Based on Approximate Logic Haruki Saito, Masayuki Arai, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Shrinking feature size and higher integration on semiconductor device manufacturing technology have shown importance of online error detection and masking to tolerate hard faults cause by manufacturing defects or ageing and soft errors. In a dependable design technique based on approximate logic circuit, a part of logic function of the target circuit is duplicated, and then a part of faults that occur can be detected or be masked. In this study we discuss two constructing scheme of approximate logic. In the first scheme based on type assignment, every logic gates is first assigned to one of four types, according to ease of propagation of logic values 0 and 1. Then the approximate logic is constructed by selecting the outputs belonging to the specific type. In the second scheme based on common term, the number of overlapping outputs is calculated for every term in the logic function, and the terms with higher overlapping ratios are selected for constructing the approximate logic. We apply the proposed constructing schemes to several benchmark circuits and 4-bit adder-subtractor, and evaluate their effectiveness in terms of hardware overhead and fault masking rate. Assuming independent and constant fault model on every gate, we also evaluate reliability for hard fault and soft error. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | approximate logic circuit / online error detection / online error masking / fault masking rate / soft error |
| Paper # | DC2014-80 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2015/2/6(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Note on Evaluation of Dependable Design Based on Approximate Logic |
| Sub Title (in English) | |
| Keyword(1) | approximate logic circuit |
| Keyword(2) | online error detection |
| Keyword(3) | online error masking |
| Keyword(4) | fault masking rate |
| Keyword(5) | soft error |
| 1st Author's Name | Haruki Saito |
| 1st Author's Affiliation | College of Industrial Technology, Nihon University() |
| 2nd Author's Name | Masayuki Arai |
| 2nd Author's Affiliation | College of Industrial Technology, Nihon University |
| Date | 2015-02-13 |
| Paper # | DC2014-80 |
| Volume (vol) | vol.114 |
| Number (no) | 446 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |