Presentation 2015-02-13
Studies on FPGA Rejuvenation
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Abstract(in English) In this paper, feasibility studies on implementing rejuvenation techniques on SRAM-based FPGAs are conducted. As a preliminary stage of the study, this paper proposes a combination of reactive and preventive rejuvenation scheme for a dual-FPGA architecture system. Techniques such as error detection and correction, rollback and re-computation are implemented to handle soft errors. Meanwhile, rejuvenation technique is used to handle firm errors. Reactive rejuvenation is triggered when a fault is detected. On the other hand, preventive rejuvenation is triggered on the basis of failure rate estimation. This can be effective to counteract silent data corruptions and errors taking longer time to manifest to the system outputs which can affect the system in the future. With the combination of an accurate failure rate estimation, this technique can be efficient and can improve the resiliency of the system.
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Keyword(in English) software aging and rejuvenation / FPGA fault tolerance / soft error rate estimation
Paper # DC2014-78
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Committee DC
Conference Date 2015/2/6(1days)
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Registration To Dependable Computing (DC)
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Studies on FPGA Rejuvenation
Sub Title (in English)
Keyword(1) software aging and rejuvenation
Keyword(2) FPGA fault tolerance
Keyword(3) soft error rate estimation
1st Author's Name Aromhack SAYSANASONGKHAM
1st Author's Affiliation Graduate School of System Design, Tokyo Metropolitan University()
2nd Author's Name Satoshi FUKUMOTO
2nd Author's Affiliation Faculty of System Design, Tokyo Metropolitan University
Date 2015-02-13
Paper # DC2014-78
Volume (vol) vol.114
Number (no) 446
Page pp.pp.-
#Pages 6
Date of Issue