| Presentation | 2015-01-30 Winner-Take-All Neural Network with DPLL Considering Scalability Masaki AZUMA, Hiroomi HIKAWA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper proposes a hardware winner-take-all neural network (WTANN) that employs a new winner-take-all (WTA) circuit with phase-modulated pulse signals and digital phase-locked loops (DPLLs). The system uses DPLL as a computing element, so all input values are expressed by phases of rectangular signals. The proposed WTA circuit employs a simple winner search circuit. The proposed WTANN architecture is described by very high speed integrated circuit (VHSIC) hardware description language (VHDL) and its feasibility was tested and verified through simulations and experiments. Conventional WTA takes a centralized winner search approach, in which vector distances are collected from all neurons and compared. In contrast, the winner search in the proposed system is carried out locally by a distributed winner search circuit among neurons. Therefore, no global communication channels with a wide bandwidth between the winner search module and each neuron are required. Furthermore, the proposed WTANN can easily extend the system scale, merely by increasing the number of neurons. The circuit size and speed were then evaluated by applying the VHDL description to a logic synthesis tool and experiments using a field programmable gate array (FPGA). Vector classifications with WTANN using two kinds of data sets, Iris and Wine, were carried out in VHDL simulations. The results revealed that the proposed WTANN achieved valid learning. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Neural Network / Winner-Take-All / DPLL / Supervised Learning |
| Paper # | NC2014-65 |
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| Committee | NC |
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| Conference Date | 2015/1/22(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Neurocomputing (NC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Winner-Take-All Neural Network with DPLL Considering Scalability |
| Sub Title (in English) | |
| Keyword(1) | Neural Network |
| Keyword(2) | Winner-Take-All |
| Keyword(3) | DPLL |
| Keyword(4) | Supervised Learning |
| 1st Author's Name | Masaki AZUMA |
| 1st Author's Affiliation | Graduate School of Science and Engineering, Kansai University() |
| 2nd Author's Name | Hiroomi HIKAWA |
| 2nd Author's Affiliation | Graduate School of Science and Engineering, Kansai University |
| Date | 2015-01-30 |
| Paper # | NC2014-65 |
| Volume (vol) | vol.114 |
| Number (no) | 437 |
| Page | pp.pp.- |
| #Pages | 6 |
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