| Presentation | 2015-01-16 Comparison of bi- and tri-level drive of CMOS class-D power amplifier in quadrature modulation type EPWM transmitter using tri-level output delta-sigma modulator Wataru Someya, Takashi Noda, Yohtaro Umeda, Yusuke Kozawa, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This study presents a characteristic comparison of power amplifier which is driven by bi- and tri-level signal using quadrature modulation type envelope pulse width modulation (EPWM) with tri-level output delta-sigma modulator. In addition, it also compare the case with and without a voltage offset to an input signal in order to reduce the through current of the class-D power amplifier and compare the case with the parallel and the series resonator at the filter in the power amplifier. As a result, it was found that the case of the tri-level input signal with offset and with the parallel resonator, is the optimum from the standpoint of view of power efficiency. In addition, the case of the bi-level input signal with offset and with the series resonator is the optimum from the stand point of view of EVM. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | transmiter / class-D power amplifier / EPWM / EVM / PAE / drain efficiency |
| Paper # | ED2014-134,MW2014-198 |
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| Conference Information | |
| Committee | ED |
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| Conference Date | 2015/1/8(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Electron Devices (ED) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Comparison of bi- and tri-level drive of CMOS class-D power amplifier in quadrature modulation type EPWM transmitter using tri-level output delta-sigma modulator |
| Sub Title (in English) | |
| Keyword(1) | transmiter |
| Keyword(2) | class-D power amplifier |
| Keyword(3) | EPWM |
| Keyword(4) | EVM |
| Keyword(5) | PAE |
| Keyword(6) | drain efficiency |
| 1st Author's Name | Wataru Someya |
| 1st Author's Affiliation | Department of Electrical Engineering, Graduate School of Science and Technology, Tokyo University of Science() |
| 2nd Author's Name | Takashi Noda |
| 2nd Author's Affiliation | Department of Electrical Engineering, Graduate School of Science and Technology, Tokyo University of Science |
| 3rd Author's Name | Yohtaro Umeda |
| 3rd Author's Affiliation | Department of Electrical Engineering, Graduate School of Science and Technology, Tokyo University of Science |
| 4th Author's Name | Yusuke Kozawa |
| 4th Author's Affiliation | Department of Electrical Engineering, Graduate School of Science and Technology, Tokyo University of Science |
| Date | 2015-01-16 |
| Paper # | ED2014-134,MW2014-198 |
| Volume (vol) | vol.114 |
| Number (no) | 391 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |