Presentation 2015-01-29
Study on Clock Tree Delay Analysis Mechanism
Goro Suzuki, Ryutaro Takeda,
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Abstract(in English) Novel delay analysis mechanism for VLSI clock tree is proposed. Proposed mechanism propagates waveform along path from VLSI clock pin to F/F, instead of solving large size ordinary differential equation like Spice^[○!R]. Using Markov Chain corresponding to interconnect circuit, Random Walk by stochastic game gives interconnect output waveform, and reduced information of propagated waveform generates buffer output waveform efficiently. Waveform level delay analysis system PD_Wave composed of proposed mechanisms can be accelerated by GPGPU. Experimental results of H-tree type clock tree showed 247x-853x acceleration vs. Spice^[○!R] with sufficient accuracy from a practical viewpoint.
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Keyword(in English) clock tree / H-tree / delay / skew / circuit reduction / Random Walk / Spice^[○!R] / GPGPU / parallel processing
Paper # VLD2014-126,CPSY2014-135,RECONF2014-59
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Committee RECONF
Conference Date 2015/1/22(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
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Title (in English) Study on Clock Tree Delay Analysis Mechanism
Sub Title (in English)
Keyword(1) clock tree
Keyword(2) H-tree
Keyword(3) delay
Keyword(4) skew
Keyword(5) circuit reduction
Keyword(6) Random Walk
Keyword(7) Spice^[○!R]
Keyword(8) GPGPU
Keyword(9) parallel processing
1st Author's Name Goro Suzuki
1st Author's Affiliation Department of Information Science, University of Kitakyushu()
2nd Author's Name Ryutaro Takeda
2nd Author's Affiliation Department of Information Science, University of Kitakyushu
Date 2015-01-29
Paper # VLD2014-126,CPSY2014-135,RECONF2014-59
Volume (vol) vol.114
Number (no) 428
Page pp.pp.-
#Pages 8
Date of Issue