Presentation 2015-01-29
Small Bandwidth Compression Hardware Exploited Distribution of Length of Prediction Residual
Tomohiro Ueno, Ryo Ito, Kentaro Sano, Satoru Yamamoto,
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Abstract(in English) This paper shows a compact bandwidth compressor to increase the performance of numerical computation on FPGA. We must reduce an area overhead of the compressor to apply to numerical computation with multiple channels. Therefore, we propose a method exploited distribution of residual length to reduce the area of barrel shifters which cause of huge hardware. We show that the proposed method achieves a decent compression ratio with very small compressor by simulation with modeled data and hardware implementation.
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Keyword(in English) Bandwidth / Data Compression / Prediction / Residual / FPGA
Paper # VLD2014-123,CPSY2014-132,RECONF2014-56
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Committee RECONF
Conference Date 2015/1/22(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Small Bandwidth Compression Hardware Exploited Distribution of Length of Prediction Residual
Sub Title (in English)
Keyword(1) Bandwidth
Keyword(2) Data Compression
Keyword(3) Prediction
Keyword(4) Residual
Keyword(5) FPGA
1st Author's Name Tomohiro Ueno
1st Author's Affiliation Graduate School of Information Sciences, Tohoku University()
2nd Author's Name Ryo Ito
2nd Author's Affiliation Graduate School of Information Sciences, Tohoku University
3rd Author's Name Kentaro Sano
3rd Author's Affiliation Graduate School of Information Sciences, Tohoku University
4th Author's Name Satoru Yamamoto
4th Author's Affiliation Graduate School of Information Sciences, Tohoku University
Date 2015-01-29
Paper # VLD2014-123,CPSY2014-132,RECONF2014-56
Volume (vol) vol.114
Number (no) 428
Page pp.pp.-
#Pages 6
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