Presentation 2015/1/22
A High Speed Logic Simulation Engine using FPGA
Natsuki Matsumoto, Michiaki Muraoka,
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Abstract(in English) In this paper, an acceleration method of a hardware algorithm of the logic simulation using the leveled method is proposed, and a prototype simulation engine based on it is developed. The acceleration algorithm consists of the high speed accessible data structure for FPGA, the parallel logic evaluation parts of the hardware algorithm and the efficient and high-speed memory access method in FPGA. The parallel logic simulation algorithm was implemented on the FPGA, and the performance of the prototype simulation engine was evaluated. As the result of the evaluation, the speed of the proposed hardware algorithm is estimated to achieve approximately 20 times faster than one of the fastest commercial logic simulator.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) FPGA / Logic Simulation / Parallel Processing / Parallel Algorithm / LSI
Paper # Vol.2015-SLDM-169 No.11
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Conference Information
Committee RECONF
Conference Date 2015/1/22(1days)
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Paper Information
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A High Speed Logic Simulation Engine using FPGA
Sub Title (in English)
Keyword(1) FPGA
Keyword(2) Logic Simulation
Keyword(3) Parallel Processing
Keyword(4) Parallel Algorithm
Keyword(5) LSI
1st Author's Name Natsuki Matsumoto
1st Author's Affiliation Information Science Division, Graduate School of Science, Kochi University()
2nd Author's Name Michiaki Muraoka
2nd Author's Affiliation Information Science Division, Graduate School of Science, Kochi University
Date 2015/1/22
Paper # Vol.2015-SLDM-169 No.11
Volume (vol) vol.114
Number (no) 428
Page pp.pp.-
#Pages 6
Date of Issue