| Presentation | 2015-01-29 Exploring 3D FPGA Architectures to Minimize the Number of Inter-layer Connections Qian ZHAO, Motoki AMAGASAKI, Masahiro IIDA, Morihiro KUGA, Toshinori SUEYOSHI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The 3D IC technology is being researched to build better performance LSIs in a variety of applications when the process miniaturization approaches its physical limitation. This technology provides shorter logics distances and high speed wide I/Os by stacking IC layers vertically. However, because of the large performance overhead of inter-layer connections, the architecture design is challenging, especially for 3D FPGAs. In this paper, in order to balance the cost and performance, and to explore 3D FPGA architectures with realistic 3D IC processes, we propose and compare spatial distributed and function distributed 3D FPGAs. The results show that when considering a two layers 3D FPGA, a face-down stacked function distributed architecture performances better. On the other hand, face-up stacked spatial distributed architectures have more advantages when building 3D FPGAs with more than two layers. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | 3D-FPGA / TSV |
| Paper # | VLD2014-120,CPSY2014-129,RECONF2014-53 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2015/1/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Exploring 3D FPGA Architectures to Minimize the Number of Inter-layer Connections |
| Sub Title (in English) | |
| Keyword(1) | 3D-FPGA |
| Keyword(2) | TSV |
| 1st Author's Name | Qian ZHAO |
| 1st Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University() |
| 2nd Author's Name | Motoki AMAGASAKI |
| 2nd Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| 3rd Author's Name | Masahiro IIDA |
| 3rd Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| 4th Author's Name | Morihiro KUGA |
| 4th Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| 5th Author's Name | Toshinori SUEYOSHI |
| 5th Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| Date | 2015-01-29 |
| Paper # | VLD2014-120,CPSY2014-129,RECONF2014-53 |
| Volume (vol) | vol.114 |
| Number (no) | 428 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |