| Presentation | 2014-12-19 Thermal Resistance Improvement and Low-resistance Lateral PIN Junction Formation Technique on III-V-OI Wafers Yuki IKKU, Mitsuru TAKENAKA, Shinichi TAKAGI, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | III-V CMOS photonics is a platform which enables strong optical confinement to the III-V waveguides by using III-V-on-Insulator (III-V-OI) wafers. III-V CMOS photonics also enables monolithic integration of passive waveguide devices and high performance active photonic devices including lasers. In this paper, we have investigated how to improve the thermal tolerance of the III-V-OI wafers and how to form low-resistance lateral p-i-n junctions on the III-V-OI wafers. We have found that the interface state between the III-V layer and the insulating layer is important for the thermal tolerance of the III-V-OI wafers. The interface state after high temperature process was found to be improved by the re-capping process and changing the bonding interface to SiO_2 from Al_2O_3. Then, we have formed lateral p-i-n junctions on the III-V-OI wafers using Si ion implantation and Zn diffusion process. By reducing the length of the 'i' layer, low resistance of 1.0 Ω・cm was obtained. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Photonic integrated circuits / Wafer bonding / Thermal tolerance / Lateral PIN junctions / III-V CMOS photonics |
| Paper # | OPE2014-146,LQE2014-133 |
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| Conference Information | |
| Committee | LQE |
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| Conference Date | 2014/12/11(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Lasers and Quantum Electronics (LQE) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Thermal Resistance Improvement and Low-resistance Lateral PIN Junction Formation Technique on III-V-OI Wafers |
| Sub Title (in English) | |
| Keyword(1) | Photonic integrated circuits |
| Keyword(2) | Wafer bonding |
| Keyword(3) | Thermal tolerance |
| Keyword(4) | Lateral PIN junctions |
| Keyword(5) | III-V CMOS photonics |
| 1st Author's Name | Yuki IKKU |
| 1st Author's Affiliation | Department of Electrical Engineering and Information Systems, University of Tokyo() |
| 2nd Author's Name | Mitsuru TAKENAKA |
| 2nd Author's Affiliation | Department of Electrical Engineering and Information Systems, University of Tokyo |
| 3rd Author's Name | Shinichi TAKAGI |
| 3rd Author's Affiliation | Department of Electrical Engineering and Information Systems, University of Tokyo |
| Date | 2014-12-19 |
| Paper # | OPE2014-146,LQE2014-133 |
| Volume (vol) | vol.114 |
| Number (no) | 378 |
| Page | pp.pp.- |
| #Pages | 4 |
| Date of Issue | |