Presentation 2014-12-02
Uniqueness Evaluation of a Current Mismatch type ID Generation Circuit
Kenichi Matsunaga, Shoichi Oshima, Tadashi Minotani, Toshihiko Kondo, Hiroki Morimura,
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Abstract(in English) This paper presents a low-power and uniquely-distributed ID-generation circuit using process variation. Developed circuit utilizes current mismatch in NMOS pair for unique ID output. In order to evaluate the output 1/0 probability-uniformity and process dependence, the prototype was fabricated in two different 0.18-μm standard CMOS technology. 382 chips were tested and the hamming distances between each chip were calculated. The result shows the circuit architecture generates unique and process-independent ID. Furthermore, the bit-generation efficiency was found to be 0.96 pJ/bit.
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Keyword(in English) ID generation / Mismatch / Hamming distance / Uniqueness / Binominal distribution / PUF
Paper # ICD2014-108,CPSY2014-120
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Committee ICD
Conference Date 2014/11/24(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Uniqueness Evaluation of a Current Mismatch type ID Generation Circuit
Sub Title (in English)
Keyword(1) ID generation
Keyword(2) Mismatch
Keyword(3) Hamming distance
Keyword(4) Uniqueness
Keyword(5) Binominal distribution
Keyword(6) PUF
1st Author's Name Kenichi Matsunaga
1st Author's Affiliation NTT Device Technology Laboratories()
2nd Author's Name Shoichi Oshima
2nd Author's Affiliation NTT Device Technology Laboratories
3rd Author's Name Tadashi Minotani
3rd Author's Affiliation NTT TELECON
4th Author's Name Toshihiko Kondo
4th Author's Affiliation NTT Device Technology Laboratories
5th Author's Name Hiroki Morimura
5th Author's Affiliation NTT TELECON
Date 2014-12-02
Paper # ICD2014-108,CPSY2014-120
Volume (vol) vol.114
Number (no) 345
Page pp.pp.-
#Pages 5
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