Presentation | 2014-12-02 Normally-Off Computing with Perpendicular STT-MRAM Hiroki NOGUCHI, Kazutaka IKEGAMI, Naoharu SHIMOMURA, Tetsufumi TANAMOTO, Junichi ITO, Shinobu FUJITA, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | This paper presents an STT-MRAM circuit design for power and area reduction of cache memory in micro-processors. The proposed STT-MRAM has three circuit techniques: memory cell, current integral sensing scheme, and dual-sensing salvation. The dual cell structure and current-integral sensing scheme are adopted for high speed read operation, and utilizes the advanced perpendicular magnetic tunnel junction (MTJ) for high speed write to achieve more than 250 MHz operation, which is suitable for cache purpose. The dual-sensing salvation scheme enhances the reliability of STT-MRAM along with typical error-correcting code (ECC). The comparison of CPU performance per power with SRAM-based, embedded DRAM and prior STT-MRAM-based LLCs indicates that the presented LLC is the most suitable for large LLC. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Spin-transfer torque / STT-MRAM / MTJ / Low power / LLC |
Paper # | ICD2014-102,CPSY2014-114 |
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Conference Information | |
Committee | ICD |
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Conference Date | 2014/11/24(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Integrated Circuits and Devices (ICD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Normally-Off Computing with Perpendicular STT-MRAM |
Sub Title (in English) | |
Keyword(1) | Spin-transfer torque |
Keyword(2) | STT-MRAM |
Keyword(3) | MTJ |
Keyword(4) | Low power |
Keyword(5) | LLC |
1st Author's Name | Hiroki NOGUCHI |
1st Author's Affiliation | Toshiba Corporation, Corporate R&D center() |
2nd Author's Name | Kazutaka IKEGAMI |
2nd Author's Affiliation | Toshiba Corporation, Corporate R&D center |
3rd Author's Name | Naoharu SHIMOMURA |
3rd Author's Affiliation | Toshiba Corporation, Corporate R&D center |
4th Author's Name | Tetsufumi TANAMOTO |
4th Author's Affiliation | Toshiba Corporation, Corporate R&D center |
5th Author's Name | Junichi ITO |
5th Author's Affiliation | Toshiba Corporation, Corporate R&D center |
6th Author's Name | Shinobu FUJITA |
6th Author's Affiliation | Toshiba Corporation, Corporate R&D center |
Date | 2014-12-02 |
Paper # | ICD2014-102,CPSY2014-114 |
Volume (vol) | vol.114 |
Number (no) | 345 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |